公开(公告)号：US5536684A

公开(公告)日：1996-07-16

申请号：US269440

申请日：1994-06-30

申请人： M. Lawrence A. Dass ,  Peng Cheng ,  David B. Fraser

发明人： M. Lawrence A. Dass ,  Peng Cheng ,  David B. Fraser

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/2257 ,  Y10S148/015 ,  Y10S148/035 ,  Y10S148/147

摘要： A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer. If the cobalt silicide layer after the ion implantation contain dopants, then during the anneal the dopants are driven out of the cobalt silicide layer and diffuse into the silicon substrate to form a conformal shallow junction. The resulting structure can be used in the vertical integration of microelectronic devices. In other words, the resulting structure is suitable for growing selective epitaxial silicon, for growing epitaxial insulators, for processing devices above the silicide in that epitaxial silicon, and for processing devices with buried conductors.

摘要翻译： 用于形成平面外延钴硅化物并形成用于半导体处理的浅共形结的方法。 形成硅化钴和氮化钛双层。 化学去除氮化钛层。 然后将具有或不具有掺杂剂的离子注入到硅化钴层中。 在离子注入期间，将至少一部分硅化钴层转变为无定形钴硅混合物，而非非晶部分保持单晶。 如果离子注入包含掺杂剂，则在注入完成之后，硅化钴层的非晶态部分和非非晶部分均含有掺杂剂。 然后将衬底在包含氮气的环境中或在氧化环境中退火。 在退火期间，硅衬底的非晶部分再结晶成单晶硅化钴层。 如果离子注入后的硅化钴层含有掺杂剂，则在退火期间，掺杂剂被驱出钴硅化物层并扩散到硅衬底中以形成共形的浅结。 所得结构可用于微电子器件的垂直集成。 换句话说，所得结构适于生长选择性外延硅，用于生长外延绝缘体，用于在该外延硅中的硅化物上方处理器件，以及用于处理具有埋入导体的器件。

公开(公告)号：US5350484A

公开(公告)日：1994-09-27

申请号：US941412

申请日：1992-09-08

申请人： Donald S. Gardner ,  Xiao-Chun Mu ,  David B. Fraser

发明人： Donald S. Gardner ,  Xiao-Chun Mu ,  David B. Fraser

IPC分类号： H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76838 ,  H01L21/32136

摘要： The present invention discloses a method for anisotropically etching metal interconnects in the fabrication of semiconductor devices, especially ULSI interconnects having high aspect ratios. A metal film is first deposited on the appropriate layer of a semiconductor substrate by techniques well-known in the art. A mask layer is deposited over the metal film with openings defined in the mask layer for patterning of the metal film. Ions are then introduced into an exposed region of the metal film to anisotropically form a converted layer of the metal film comprising compounds of the metal. The introduction of the ions into the metal film can be performed by conventional methods, such as through the use of a reactive ion etch system or an ion implantation system, or by any other method which anisotropically forms the metal compounds. The mask layer is then removed by conventional means to leave behind the metal film having a converted layer of metal compounds. Finally, the metal compounds are selectively removed by a suitable removal means chosen for its properties in removing the metal compounds without causing significant etching or degradation of the metal film itself.

摘要翻译： 本发明公开了一种在半导体器件制造中各向异性蚀刻金属互连的方法，特别是具有高纵横比的ULSI互连。 首先通过本领域公知的技术将金属膜沉积在半导体衬底的适当层上。 掩模层沉积在具有限定在掩模层中的开口的金属膜上，用于图案化金属膜。 然后将离子引入到金属膜的暴露区域中以各向异性地形成包含金属化合物的金属膜的转化层。 将离子引入金属膜可以通过常规方法进行，例如通过使用反应离子蚀刻系统或离子注入系统，或通过各向异性形成金属化合物的任何其它方法来进行。 然后通过常规方法除去掩模层，留下具有转化层金属化合物的金属膜。 最后，金属化合物通过合适的去除手段被选择性地除去，因为其去除金属化合物的性质而不引起金属膜本身的显着蚀刻或降解。

公开(公告)号：US06790704B2

公开(公告)日：2004-09-14

申请号：US09908016

申请日：2001-07-17

申请人： Brian Doyle ,  Quat T. Vu ,  David B. Fraser

发明人： Brian Doyle ,  Quat T. Vu ,  David B. Fraser

IPC分类号： H01L2144

CPC分类号： H01L23/642 ,  H01L23/48 ,  H01L25/18 ,  H01L2224/16

摘要： A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.

摘要翻译： 描述了将第一半导体衬底上的第一组导电焊盘电耦合到第二半导体衬底上的第二组导电焊盘的方法。 第一厚度的介电材料沉积在至少一组第一和第二组导电焊盘上。 然后将第一和第二半导体衬底附接在一起，使得第一组和第二组衬垫基本上彼此平行对准，并且使得电介质材料设置在第一组和第二组导电衬垫之间。

公开(公告)号：US6040628A

公开(公告)日：2000-03-21

申请号：US769549

申请日：1996-12-19

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/58

CPC分类号： H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002

摘要： A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer. Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.

摘要翻译： 描述了一种制造半导体集成电路的结构和方法。 第一图案化导电层在图案的沟槽内包含低介电常数的第一绝缘材料，例如有机聚合物。 在第一图案化导电层上形成第二绝缘材料，例如具有比第一绝缘材料更大的机械强度和导热性以及更高介电常数的二氧化硅或其它绝缘材料。 填充有导电插塞的第二绝缘材料内的通孔和第二图案化的导电层可以形成在第二绝缘材料上。 该结构可以根据需要重复多次以形成完整的集成电路。

公开(公告)号：US5977634A

公开(公告)日：1999-11-02

申请号：US954221

申请日：1997-10-20

申请人： Gang Bai ,  David B. Fraser

发明人： Gang Bai ,  David B. Fraser

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76864 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76834

摘要： An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.

摘要翻译： 包括扩散阻挡层的电互连结构和在半导体衬底上形成结构的方法。 在衬底上形成双层扩散阻挡层。 屏障包括阻挡层下面的捕获层。 阻挡层比捕获层厚，并且与捕获层不反应。 然后在阻挡层上形成比阻挡层厚的导电层。 当导电层与阻挡层的阻挡层不反应时，导电层与屏障的捕获层是反应的。

公开(公告)号：US5861340A

公开(公告)日：1999-01-19

申请号：US602126

申请日：1996-02-15

申请人： Gang Bai ,  David B. Fraser

发明人： Gang Bai ,  David B. Fraser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L29/4941 ,  H01L29/665

摘要： A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

摘要翻译： 一种形成多硅化物薄膜的方法。 首先，形成硅层。 接下来，在第一硅层上形成薄的阻挡层。 然后在阻挡层上形成第二硅层。 接下来，在第二硅层上形成金属层。 然后金属层和第二硅层一起反应形成硅化物。

公开(公告)号：US5625217A

公开(公告)日：1997-04-29

申请号：US384352

申请日：1995-02-02

申请人： Robert S. Chau ,  David B. Fraser ,  Kenneth C. Cadien ,  Gopal Raghavan ,  Leopoldo D. Yau

发明人： Robert S. Chau ,  David B. Fraser ,  Kenneth C. Cadien ,  Gopal Raghavan ,  Leopoldo D. Yau

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002

摘要： A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

摘要翻译： 一种具有与标准CMOS制造工艺兼容的复合栅电极的新颖可靠的高性能MOS晶体管。 复合栅电极包括形成在高导电层上的多晶硅层。 复合栅电极形成在形成在硅衬底上的栅极绝缘层上。 在衬底中形成一对源极/漏极区，并且与复合栅电极的外边缘自对准。

公开(公告)号：US4966868A

公开(公告)日：1990-10-30

申请号：US406881

申请日：1989-09-13

申请人： Venkatesan Murali ,  Chih-Shih Wei ,  David B. Fraser

发明人： Venkatesan Murali ,  Chih-Shih Wei ,  David B. Fraser

IPC分类号： H01L21/285 ,  H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/28525

摘要： A process which provides for self-aligned contact hole filling leading to complete planarization and low contact resistance at the same time, without the use of additional lithographic masking procedures is described. Further, the resultant conductive plug eliminates spiking problems between aluminum and silicon during a subsequent alloying process. In an embodiment, a selective polysilicon layer is deposited and appropriately doped; a second undoped selective silicon layer is then deposited, followed by a refractory metal layer, These layers are heated to produce a self-aligned refractory metal silicide plug.

摘要翻译： 描述了一种提供自对准接触孔填充的过程，导致完全平坦化和同时具有低接触电阻，而不使用额外的光刻掩模程序。 此外，所得到的导电插塞在随后的合金化过程中消除了铝和硅之间的尖峰问题。 在一个实施例中，选择性多晶硅层被沉积并适当掺杂; 然后沉积第二未掺杂的选择性硅层，然后沉积难熔金属层。将这些层加热以产生自对准难熔金属硅化物塞。

公开(公告)号：US4244799A

公开(公告)日：1981-01-13

申请号：US941369

申请日：1978-09-11

申请人： David B. Fraser ,  Dan Maydan ,  Joseph M. Moran

发明人： David B. Fraser ,  Dan Maydan ,  Joseph M. Moran

IPC分类号： H01L21/302 ,  G03F7/09 ,  H01L21/027 ,  H01L21/30 ,  H01L21/306 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205

CPC分类号： H01L21/0274 ,  G03F7/094 ,  H01L21/0277 ,  H01L21/0278 ,  H01L21/312

摘要： In an integrated circuit fabrication sequence, a relatively thick sacrificial layer (18) is deposited on a nonplanar surface of a device wafer in which high-resolution features are to be defined. The thick layer is characterized by a conforming lower surface and an essentially planar top surface and by the capability of being patterned in a high-resolution way. An intermediate masking layer (22) and then a thin resist layer (20) are deposited on the top surface of the sacrificial layer, the thickness of the resist layer being insufficient by itself to provide adequate step coverage if the resist layer were applied directly on the nonplanar surface. A high-resolution pattern defined in the resist layer is transferred into the intermediate masking layer. Subsequently, a dry processing technique is utilized to replicate the pattern in the sacrificial layer. A high-resolution pattern with near-vertical sidewalls is thereby produced in the sacrificial layer. By means of the patterned sacrificial layer, high-resolution features are then defined in the underlying nonplanar surface.

摘要翻译： 在集成电路制造序列中，相对较厚的牺牲层（18）沉积在要限定高分辨率特征的器件晶片的非平面表面上。 厚层的特征在于具有一致的下表面和基本平坦的顶表面，并且通过以高分辨率方式图案化的能力。 中间掩模层（22）然后薄的抗蚀剂层（20）沉积在牺牲层的顶表面上，抗蚀剂层的厚度本身不足以提供足够的阶梯覆盖，如果抗蚀剂层直接施加在 非平面。 在抗蚀剂层中限定的高分辨率图案被转移到中间掩模层中。 随后，使用干法处理技术来复制牺牲层中的图案。 由此在牺牲层中产生具有近垂直侧壁的高分辨率图案。 通过图案化的牺牲层，然后在下面的非平面表面中定义高分辨率特征。

公开(公告)号：US06777320B1

公开(公告)日：2004-08-17

申请号：US09191930

申请日：1998-11-13

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L214763

CPC分类号： H01L23/5222 ,  H01L21/76837 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for microelectronic devices includes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.

摘要翻译： 用于微电子器件的互连结构包括多个图案化的，间隔开的基本共平面的导电线，多条导线的第一部分具有第一介电常数介于第一介电常数之间，第二部分为 多个导电线具有第二介电常数介于其间的第二介电常数。 通过提供介电常数的面内可选择性，可以增加在电源节点之间的平面内去耦电容，而可以减小信号线之间的面内寄生电容。