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25 条记录 (耗时 0.029 秒)

    Method for the anisotropic etching of metal films in the fabrication of interconnects
    1.
    发明授权
    Method for the anisotropic etching of metal films in the fabrication of interconnects 失效
    互连制造中各向异性蚀刻金属膜的方法

    公开(公告)号：US5350484A

    公开(公告)日：1994-09-27

    申请号：US941412

    申请日：1992-09-08

    申请人： Donald S. Gardner ,  Xiao-Chun Mu ,  David B. Fraser

    发明人： Donald S. Gardner ,  Xiao-Chun Mu ,  David B. Fraser

    IPC分类号： H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/00

    CPC分类号： H01L21/76838 ,  H01L21/32136

    摘要： The present invention discloses a method for anisotropically etching metal interconnects in the fabrication of semiconductor devices, especially ULSI interconnects having high aspect ratios. A metal film is first deposited on the appropriate layer of a semiconductor substrate by techniques well-known in the art. A mask layer is deposited over the metal film with openings defined in the mask layer for patterning of the metal film. Ions are then introduced into an exposed region of the metal film to anisotropically form a converted layer of the metal film comprising compounds of the metal. The introduction of the ions into the metal film can be performed by conventional methods, such as through the use of a reactive ion etch system or an ion implantation system, or by any other method which anisotropically forms the metal compounds. The mask layer is then removed by conventional means to leave behind the metal film having a converted layer of metal compounds. Finally, the metal compounds are selectively removed by a suitable removal means chosen for its properties in removing the metal compounds without causing significant etching or degradation of the metal film itself.

    摘要翻译： 本发明公开了一种在半导体器件制造中各向异性蚀刻金属互连的方法，特别是具有高纵横比的ULSI互连。 首先通过本领域公知的技术将金属膜沉积在半导体衬底的适当层上。 掩模层沉积在具有限定在掩模层中的开口的金属膜上，用于图案化金属膜。 然后将离子引入到金属膜的暴露区域中以各向异性地形成包含金属化合物的金属膜的转化层。 将离子引入金属膜可以通过常规方法进行，例如通过使用反应离子蚀刻系统或离子注入系统，或通过各向异性形成金属化合物的任何其它方法来进行。 然后通过常规方法除去掩模层，留下具有转化层金属化合物的金属膜。 最后，金属化合物通过合适的去除手段被选择性地除去，因为其去除金属化合物的性质而不引起金属膜本身的显着蚀刻或降解。

    Methods of forming an interconnect on a semiconductor substrate
    2.
    发明授权
    Methods of forming an interconnect on a semiconductor substrate 失效
    在半导体衬底上形成互连的方法

    公开(公告)号：US5612254A

    公开(公告)日：1997-03-18

    申请号：US905473

    申请日：1992-06-29

    申请人： Xiao-Chun Mu ,  Srinivasan Sivaram ,  Donald S. Gardner ,  David B. Fraser

    发明人： Xiao-Chun Mu ,  Srinivasan Sivaram ,  Donald S. Gardner ,  David B. Fraser

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1036 ,  H01L2924/0002

    摘要： A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

    摘要翻译： 描述了在半导体器件中的预制图形通道内形成互连的装置和方法。 本发明包括在半导体器件内形成互连通道的方法。 第一电介质层沉积在衬底上并被图案化以形成随后用接触插塞填充的接触开口。 在图案化的第一介电层和接触插塞上沉积第二介电层。 图案化第二电介质层以形成互连通道，其中第一介电层用作蚀刻停止件以防止蚀刻基板。 本发明还包括形成互连的方法。 将电介质层沉积在衬底上并图案化以形成互连教堂。 金属层沉积在图案化的介电层上并且在互连通道内。 金属层用碱性溶液抛光以除去不在互连教堂内的金属层以形成互连。 本发明还包括在氮化硅层上形成互连的方法。 氮化硅层沉积在半导体衬底上并被图案化以形成随后用导电材料填充的接触开口。 金属层沉积在图案化的氮化硅层和接触插塞上，并被图案化以形成互连，使得所有互连都位于接触插塞和图案化的氮化硅层的一部分上。

    Flip-chip on flex for high performance packaging applications
    6.
    发明授权
    Flip-chip on flex for high performance packaging applications 有权
    用于高性能封装应用的Flip-chip for flex

    公开(公告)号：US06365962B1

    公开(公告)日：2002-04-02

    申请号：US09538327

    申请日：2000-03-29

    申请人： Chunlin Liang ,  Larry Eugene Mosley ,  Xiao-Chun Mu

    发明人： Chunlin Liang ,  Larry Eugene Mosley ,  Xiao-Chun Mu

    IPC分类号： H01L23495

    CPC分类号： H01L25/18 ,  H01L23/5387 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4623 ,  H01L2924/00 ,  H01L2224/0401

    摘要： According to an embodiment of the invention, an integrated circuit (IC) package is provided that includes a flexible circuit board that has a first surface and a second surface. An integrated circuit mounted to the first surface of the flexible circuit board is provided. An electrical element is attached to the second surface of the flexible circuit board. Also, an encapsulant is attached to the flexible circuit board and the integrated circuit. The flexible circuit board includes at least one layer of dielectric that is no greater than approximately 35 microns thick. In another embodiment, the integrated circuit and the electrical element may be interchanged. A method is provided including attaching an encapsulant to an IC, forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, and attaching the substrate to the encapsulant so that the substrate is connected to the IC. Also, an electrical element may be attached with a flip-chip C4 (controlled collapsed chip connection) process.

    摘要翻译： 根据本发明的实施例，提供了一种集成电路（IC）封装，其包括具有第一表面和第二表面的柔性电路板。 提供安装到柔性电路板的第一表面的集成电路。 电元件附接到柔性电路板的第二表面。 此外，密封剂附接到柔性电路板和集成电路。 柔性电路板包括不大于约35微米厚的至少一层电介质。 在另一个实施例中，集成电路和电气元件可以互换。 提供了一种方法，包括将密封剂附着到IC，从至少一层电介质形成衬底，将至少一个电接触附接到衬底，以及将衬底附接到密封剂，使得衬底连接到IC。 此外，电元件可以用倒装芯片C4（受控的塌陷芯片连接）工艺附接。

    Novel etch back process for tungsten contact/via filling
    7.
    发明授权
    Novel etch back process for tungsten contact/via filling 失效
    钨接触/通孔填充的新型回蚀工艺

    公开(公告)号：US5035768A

    公开(公告)日：1991-07-30

    申请号：US560988

    申请日：1990-07-30

    申请人： Xiao-Chun Mu ,  Jagir Multani

    发明人： Xiao-Chun Mu ,  Jagir Multani

    IPC分类号： C23F4/00 ,  H01L21/3213 ,  H01L21/768

    CPC分类号： C23F4/00 ,  H01L21/32136 ,  H01L21/7684

    摘要： An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.

    摘要翻译： 用于蚀刻形成在半导体衬底上的难熔金属层，具有大大降低的微负载效应的回蚀工艺。 蚀刻在三个步骤中进行。 第一步是使用SF6，O2和He的气体化学物质的均匀蚀刻，并且进行预定时间以去除大部分金属层。 第二步是使用SF6，Cl2和He的气体化学物质的非常均匀的蚀刻，并继续进行直到检测到端点。 通过测量和整合Cl的772nm和775nm线来检测终点。 第三步是利用Cl2和He的气体化学进行的定时蚀刻，其用作保护完全去除难熔金属膜的过滤材料，以及作为去除粘附底层的选择性蚀刻剂。

    Stacked ferroelectric memory device and method of making same
    8.
    发明授权
    Stacked ferroelectric memory device and method of making same 失效
    堆叠铁电存储器件及其制造方法

    公开(公告)号：US06960479B2

    公开(公告)日：2005-11-01

    申请号：US09960125

    申请日：2001-09-21

    申请人： Jian Li ,  Xiao-Chun Mu

    发明人： Jian Li ,  Xiao-Chun Mu

    IPC分类号： G11C11/22 ,  H01L21/00 ,  H01L27/28 ,  H01L31/113 ,  H01L31/119 ,  H01R4/24 ,  H01R13/648 ,  H01R33/02 ,  H01R39/00

    CPC分类号： G11C11/22 ,  B82Y10/00 ,  H01L27/285

    摘要： The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures. Combining ferroelectric polymer and ferroelectric oxide layers on the pre-fabricated silicon substrate cavity forms a multi-rank structure.

    摘要翻译： 铁电聚合物储存装置技术领域本发明涉及一种铁电聚合物储存装置，其包括至少两个层叠的铁电聚合物存储结构，它们被排列在至少两个相应堆叠的拓扑结构之上，该拓扑结构是包括层间电介质层和通孔结构的预制硅衬底腔。 在预制的硅衬底空腔上组合铁电聚合物和铁电氧化物层形成多级结构。

    Active interposer technology for high performance CMOS packaging application
    9.
    发明授权
    Active interposer technology for high performance CMOS packaging application 有权
    高性能CMOS封装应用的主动插入式技术

    公开(公告)号：US06600364B1

    公开(公告)日：2003-07-29

    申请号：US09225418

    申请日：1999-01-05

    申请人： Chunlin Liang ,  Xiao-Chun Mu

    发明人： Chunlin Liang ,  Xiao-Chun Mu

    IPC分类号： H01L2500

    CPC分类号： H01L23/50 ,  G11C7/02 ,  H01L23/49827 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599

    摘要： An integrated circuit assembly that includes an integrated circuit which is connected to an interposer. The integrated circuit may include a logic circuit which generates an output signal. The interposer may include a driver circuit that regenerates the output signal. The interposer may also contain a clock signal that is connected to the logic circuit. Separating the driver circuit from the integrated circuit may provide an assembly which reduces the amount of noise in the logic circuit created by the driver circuit switching states. Additionally, providing the clock circuit on the interposer allows the clock to be fabricated with a more robust process than the logic circuit of the integrated circuit.

    摘要翻译： 一种集成电路组件，其包括连接到插入器的集成电路。 集成电路可以包括产生输出信号的逻辑电路。 插入器可以包括再生输出信号的驱动器电路。 插入器还可以包含连接到逻辑电路的时钟信号。 将驱动器电路与集成电路分离可以提供一种组件，其减少由驱动器电路切换状态产生的逻辑电路中的噪声量。 此外，在插入器上提供时钟电路允许使用比集成电路的逻辑电路更稳健的处理来制造时钟。