公开(公告)号：US07899990B2

公开(公告)日：2011-03-01

申请号：US11559192

申请日：2006-11-13

申请人： Laurent R. Moll ,  Seungyoon Peter Song ,  Peter N. Glaskowsky ,  Yu Qing Cheng

发明人： Laurent R. Moll ,  Seungyoon Peter Song ,  Peter N. Glaskowsky ,  Yu Qing Cheng

IPC分类号： G06F13/00

CPC分类号： G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0802 ,  G06F12/0888 ,  G06F2212/2515 ,  Y02D10/13 ,  Y02D10/14

摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

摘要翻译： 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下，当CPU开始在低功率状态下运行时，与缓存/存储器相关的特定物理地址范围匹配或具有访问本身的特定特性的非缓存访问（例如由DMA设备生成） 微型缓存，而不是由存储器控制器和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。 在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。

公开(公告)号：US06957323B2

公开(公告)日：2005-10-18

申请号：US10004338

申请日：2001-11-14

申请人： Seungyoon Peter Song

发明人： Seungyoon Peter Song

IPC分类号： G06F9/30 ,  G06F9/38 ,  G08F12/00

CPC分类号： G06F9/30167 ,  G06F9/3009 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851

摘要： This disclosure describes an operand file, a device that combines the functions of a register file, a reservation station, and a rename buffer into single storage element. The advantage of this mechanism is that it eliminates copying results and operands between the register file, reservation station, and rename buffer, thereby greatly simplifying the design and reducing area and power consumption. Furthermore, it can also be used in multithreaded processors that spawn children threads by copying some or all of the parent thread's registers to each of the children thread's registers.

摘要翻译： 本公开描述了操作数文件，将寄存器文件，保留站和重命名缓冲器的功能组合成单个存储元件的设备。 该机制的优点在于它消除了寄存器文件，保留站和重命名缓冲区之间的复制结果和操作数，从而大大简化了设计并减少了面积和功耗。 此外，它还可以用于通过将部分或全部父线程的寄存器复制到每个子线程的寄存器来生成子线程的多线程处理器中。

公开(公告)号：US6041167A

公开(公告)日：2000-03-21

申请号：US508121

申请日：1995-07-27

申请人： Seungyoon Peter Song

发明人： Seungyoon Peter Song

IPC分类号： G06F15/00 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A processing system and method of operation are provided. A particular instruction is dispatched to execution circuitry for execution. After dispatching the particular instruction, an execution serialized instruction is dispatched to the execution circuitry prior to finishing execution of the particular instruction.

摘要翻译： 提供了一种处理系统和操作方法。 特定指令被发送到执行电路执行。 在分派特定指令之后，在执行特定指令之前将执行序列化指令分派到执行电路。

公开(公告)号：US5893930A

公开(公告)日：1999-04-13

申请号：US678940

申请日：1996-07-12

申请人： Seungyoon Peter Song

发明人： Seungyoon Peter Song

IPC分类号： G06F12/10

CPC分类号： G06F12/1027

摘要： A method for performing predictive translation of a data address in a computer processing system includes organizing a translation lookaside buffer in a set associative manner having each set associated with multiple entries, wherein the multiple entries store consecutively ordered selections. Further, the method includes selecting a set of entries in the translation lookaside buffer in response to a base operand for the predictive translation. The method also includes comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed. The method further includes the step of adding the base operand with an offset operand to produce the effective address. A system in accordance with the present invention includes effective address generation logic, including a base operand register to hold a base operand, and a translation lookaside buffer, translation lookaside buffer. The translation lookaside buffer includes a multiple number of entries organized in a set associative manner to map a desired number of consecutive pages into a single set, and coupled to the effective address generation logic to utilize selected bits of the base operand for selection of a set of entries and for comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed.

摘要翻译： 一种用于在计算机处理系统中执行数据地址的预测转换的方法包括以具有与多个条目相关联的每个集合的集合关联方式组织翻译后备缓冲器，其中所述多个条目存储连续排序的选择。 此外，该方法包括响应于用于预测性翻译的基本操作数，在翻译后备缓冲器中选择一组条目。 该方法还包括将所选集合中的每个条目与用于确定预测性翻译是否失败的输入地址进行比较。 该方法还包括将基本操作数与偏移操作数相加以产生有效地址的步骤。 根据本发明的系统包括有效地址生成逻辑，包括用于保存基本操作数的基本操作数寄存器和翻译后备缓冲器，翻译后备缓冲器。 翻译后备缓冲器包括以组合关联方式组织的多个条目，以将期望数量的连续页映射到单个集合中，并且耦合到有效地址生成逻辑，以利用用于选择集合的基本操作数的所选位 并且用于将所选集合中的每个条目与用于确定预测性翻译是否失败的输入地址进行比较。

公开(公告)号：US5838984A

公开(公告)日：1998-11-17

申请号：US697086

申请日：1996-08-19

申请人： Le Trong Nguyen ,  Seungyoon Peter Song ,  Moataz A. Mohamed ,  Heonchul Park ,  Roney Sau Don Wong

发明人： Le Trong Nguyen ,  Seungyoon Peter Song ,  Moataz A. Mohamed ,  Heonchul Park ,  Roney Sau Don Wong

IPC分类号： G06F17/16 ,  G06F9/30 ,  G06F9/318 ,  G06F12/00 ,  G06F15/16 ,  G06F15/78

CPC分类号： G06F9/30025 ,  G06F15/8076 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189

摘要： A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.

摘要翻译： 向量处理器包括两组向量寄存器，其中每个向量寄存器可以存储多个数据元素，一个控制寄存器具有指示默认库的字段。 用于向量处理器的指令集包括使用寄存器编号来识别默认组中的向量寄存器的指令，使用寄存器编号来识别包括来自第一组的寄存器的双倍大小向量寄存器和来自第二组的寄存器 ，以及包括存储位和寄存器号以用于从任一个存储体访问向量寄存器的指令。

公开(公告)号：US5664215A

公开(公告)日：1997-09-02

申请号：US622159

申请日：1996-03-27

申请人： David P. Burgess ,  Marvin Denman ,  Milton M. Hood, Jr. ,  Mark A. Kearney ,  Lavanya Kling ,  Graham R. Murphy ,  Seungyoon Peter Song

发明人： David P. Burgess ,  Marvin Denman ,  Milton M. Hood, Jr. ,  Mark A. Kearney ,  Lavanya Kling ,  Graham R. Murphy ,  Seungyoon Peter Song

IPC分类号： G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.

摘要翻译： 所公开的数据处理器（10）作为一系列简单的加载或存储指令来调度加载/存储多个并将加载/存储字符串指令加载/存储单元（28）。 定序器单元（18）分配加载/存储单元写入每个简单加载指令的数据的重命名缓冲器（34）的条目。 该策略有助于提前进行数据转发以便后续指令。 相反，如果定序器单元不能提供简单存储指令的操作数，则将重命名缓冲器标签提供给加载/存储单元。

公开(公告)号：US08281308B1

公开(公告)日：2012-10-02

申请号：US11933199

申请日：2007-10-31

申请人： Yu Qing Cheng ,  John Gregory Favor ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

发明人： Yu Qing Cheng ,  John Gregory Favor ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

IPC分类号： G06F9/455

CPC分类号： G06F9/455 ,  G06F9/4825 ,  Y02D10/24

摘要： A virtual core management system including a first physical core and a second physical core, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a first temperature sensor configured to sense a temperature of the first physical core and a second temperature sensor configured to sense a temperature of the second physical core, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the temperature of the first physical core and the temperature of the second physical core.

摘要翻译： 包括第一物理核心和第二物理核心的虚拟核心管理系统以及包括与执行程序相关联的逻辑状态的集合的虚拟核心。 虚拟核心管理系统还包括配置成感测第一物理核心的温度的第一温度传感器和被配置为感测第二物理核心的温度的第二温度传感器，以及配置成将虚拟核心映射到 基于第一物理核心的温度和第二物理核心的温度中的至少一个的第一物理核心和第二物理核心之一。

公开(公告)号：US08219788B1

公开(公告)日：2012-07-10

申请号：US11933267

申请日：2007-10-31

申请人： Yu Qing Cheng ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

发明人： Yu Qing Cheng ,  Peter N. Glaskowsky ,  Carlos Puchol ,  Seungyoon Peter Song

IPC分类号： G06F9/00

CPC分类号： G06F9/455 ,  G06F9/4825 ,  Y02D10/24

摘要： A virtual core management system including a first physical core having a first utilization constraint, a second physical core having a second utilization constraint, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a utilization indicator configured to measure a utilization of the first physical core with respect to the first utilization constraint and measure a utilization of the second physical core with respect to the second utilization constraint, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the utilization of the first physical core and the utilization of the second physical core.

摘要翻译： 一种虚拟核心管理系统，包括具有第一利用约束的第一物理核心，具有第二利用约束的第二物理核心和包括与执行程序相关联的逻辑状态的集合的虚拟核心。 所述虚拟核心管理系统还包括利用指示器，其被配置为测量所述第一物理核心相对于所述第一利用约束的利用率并且测量所述第二物理核心相对于所述第二利用约束的利用率，以及虚拟核心管理组件 被配置为基于所述第一物理核心的利用和所述第二物理核心的利用中的至少一个来将所述虚拟核心映射到所述第一物理核心和所述第二物理核心之一。

公开(公告)号：US07788473B1

公开(公告)日：2010-08-31

申请号：US11646008

申请日：2006-12-26

申请人： Chris Nelson ,  Matthew Ashcraft ,  John Gregory Favor ,  Seungyoon Peter Song

发明人： Chris Nelson ,  Matthew Ashcraft ,  John Gregory Favor ,  Seungyoon Peter Song

IPC分类号： G06F9/30

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3861

摘要： Prediction of data values to be read from memory by a microprocessor for load operations. In one aspect, a method for predicting a data value that will result from a load operation to be executed by the microprocessor includes accessing an entry in a load value prediction table that stores a predicted data value corresponding to the load operation. The predicted data value is stored in a physical storage destination of the microprocessor to be available as a result of the load operation without waiting for execution of the load operation to complete. The storage destination is the destination for a loaded data value resulting from executing the load operation.

摘要翻译： 预测由微处理器从存储器读取的数据值以进行加载操作。 一方面，用于预测由微处理器执行的加载操作产生的数据值的方法包括访问存储与加载操作对应的预测数据值的载入值预测表中的条目。 预测数据值被存储在微处理器的物理存储目的地中，作为加载操作的结果可用，而不等待执行加载操作完成。 存储目的地是由执行加载操作产生的加载数据值的目的地。

公开(公告)号：US6094705A

公开(公告)日：2000-07-25

申请号：US266072

申请日：1999-03-10

申请人： Seungyoon Peter Song

发明人： Seungyoon Peter Song

IPC分类号： G11C11/406 ,  G11C11/403

CPC分类号： G11C11/406

摘要： A method and system for selective refresh for a memory array is disclosed. The method and system comprises providing a plurality of valid bits, each of the valid bits being associated with a row of the memory device; and detecting when data access is performed within a row of the device. The method and system further comprises setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for the refresh period. By providing the valid bits in the refresh controller and associating them with a row of the memory array then if a cell is written or read at least once a duration equivalent to a refresh period, then the cells do not need to be refreshed. When a DRAM cell is accessed (read or written), its charge is fully restored so that it does not need refresh for a duration equivalent to a refresh interval. In applications that use DRAMs to repeatedly write and read data, such as frame buffers in display systems, the DRAM cells may be accessed frequently enough so that the cells may not need to be refreshed at all. If the cells are written or read at least once in a duration equivalent to a refresh period, then they do not need to be refreshed. Accordingly, through the use of the present invention power consumption is significantly reduced.

摘要翻译： 公开了用于存储器阵列的选择性刷新的方法和系统。 该方法和系统包括提供多个有效位，每个有效位与存储器件的一行相关联; 以及检测何时在设备的行内执行数据访问。 该方法和系统还包括设置相关联的有效位，相关联的有效位的设置提供该行不需要刷新刷新周期的指示。 通过在刷新控制器中提供有效位并将它们与存储器阵列的行相关联，然后如果单元被写入或读取至少等于刷新周期的持续时间，那么单元不需要刷新。 当DRAM单元被访问（读取或写入）时，其电荷被完全恢复，使得它不需要刷新持续时间等于刷新间隔。 在使用DRAM重复写入和读取数据（例如显示系统中的帧缓冲器）的应用中，可以频繁地访问DRAM单元，使得单元可能根本不需要刷新。 如果单元在等于刷新周期的持续时间内写入或读取至少一次，则不需要刷新它们。 因此，通过使用本发明，功耗明显降低。