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21.发明授权Structure and method for ultra-scalable hybrid DRAM cell with contacted P-well 失效具有接触P阱的超可扩展混合DRAM单元的结构和方法公开(公告)号：US06441422B1
公开(公告)日：2002-08-27
申请号：US09706482
申请日：2000-11-03
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867
摘要： An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.
摘要翻译： 提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。 超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。 超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。
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公开(公告)号：US06440793B1
公开(公告)日：2002-08-27
申请号：US09757514
申请日：2001-01-10
IPC分类号： H01L218242
CPC分类号： H01L27/10841 , H01L21/2255 , H01L21/26586 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
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23.发明授权Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效在单元中并联连接沟槽电容器的多端口存储器制造方法公开(公告)号：US07785959B2
公开(公告)日：2010-08-31
申请号：US12316748
申请日：2008-12-16
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。
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公开(公告)号：US07190042B2
公开(公告)日：2007-03-13
申请号：US10722353
申请日：2003-11-25
IPC分类号： H01L21/336 , H01L29/00
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically align to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要翻译： 通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。 氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。 衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。 合并的氧化物区域是自对准的，因为它们在合并在一起时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。 瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。
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25.发明授权Memory cell with vertical transistor and trench capacitor with reduced burried strap 有权具有垂直晶体管和沟槽电容器的存储单元，具有减少的挂带公开(公告)号：US06759702B2
公开(公告)日：2004-07-06
申请号：US10261559
申请日：2002-09-30
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L29/66181 , H01L29/945
摘要： A memory cell structure including a semiconductor substrate, a deep (e.g., longitudinal) trench in the semiconductor substrate, the deep trench having a plurality of sidewalls and a bottom, a buried strap along a sidewall of the deep trench, a storage capacitor at the bottom of the deep trench, a vertical transistor extending down the sidewall of the deep trench above the storage capacitor, the transistor having a diffusion extending in the plane of the substrate adjacent the deep trench, a collar oxide extending down another sidewall of the deep trench opposite the capacitor, shallow trench isolation regions extending along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends, a gate conductor extending within the deep trench, a wordline extending over the deep trench and connected to the gate conductor, and a bitline extending above the surface plane of the substrate having a contact to the diffusion between the shallow trench isolation regions. The deep trench has a perimeter in a direction normal to its depth, and the buried strap extends a distance along the perimeter, the distance being only within a range of 5% to 20% of the entire linear distance along the perimeter, and being less than one lithographic feature size. Preferably, the strap in a direction along the perimeter is curved and is disposed along only one corner of the perimeter. The structure is particularly useful for a sub-8F2 cell.
摘要翻译： 一种存储单元结构，包括半导体衬底，半导体衬底中的深（例如，纵向）沟槽，深沟槽具有多个侧壁和底部，沿着深沟槽的侧壁的掩埋带，存储电容器 深沟槽的底部，垂直晶体管，沿着存储电容器上方的深沟槽的侧壁向下延伸，晶体管具有在衬底的与深沟槽相邻的平面中延伸的扩散，从深沟槽的另一个侧壁延伸的环状氧化物 与电容器相对的浅沟槽隔离区域沿垂直于垂直晶体管延伸的侧壁横向的衬底表面延伸，在深沟槽内延伸的栅极导体，延伸在深沟槽上并与栅极导体连接的字线 以及在衬底的表面平面上方延伸的位线，该位线与浅沟槽iso之间的扩散接触 国际地区。 深沟槽在垂直于其深度的方向上具有周长，并且掩埋带沿着周边延伸一段距离，该距离仅在沿着周边的整个线性距离的5％至20％的范围内，并且更小 比一个光刻特征尺寸。 优选地，沿着周边的方向上的带子是弯曲的并且沿着周边的一个角部设置。 该结构对于亚8F 2细胞特别有用。
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26.发明授权公开(公告)号：US06339241B1
公开(公告)日：2002-01-15
申请号：US09602426
申请日：2000-06-23
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.
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公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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公开(公告)号：US06693041B2
公开(公告)日：2004-02-17
申请号：US09885790
申请日：2001-06-20
IPC分类号： H01L21311
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要翻译： 通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。 氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。 衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。 合并的氧化物区域是自对准的，因为它们在合成时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。 瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。
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公开(公告)号：US06376324B1
公开(公告)日：2002-04-23
申请号：US09602969
申请日：2000-06-23
IPC分类号： H01L2120
CPC分类号： H01L27/10867
摘要： Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.
摘要翻译： 公开了一种提供新的深沟槽套环工艺的方法，其减少了半导体器件中的阵列金属氧化物半导体场效应晶体管（MOSFET）上带扩散的侵入。 通过使MOSFET栅极导体和深沟槽存储电容器之间的距离最大化，本发明允许在深沟槽顶部减少有效的深沟槽边缘偏压，而不损害存储电容。
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