公开(公告)号：US20080132057A1

公开(公告)日：2008-06-05

申请号：US11757022

申请日：2007-06-01

申请人： Frank Feustel ,  Carsten Peters ,  Thomas Foltyn

发明人： Frank Feustel ,  Carsten Peters ,  Thomas Foltyn

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844

摘要： By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom of a via in advanced metallization structures of highly scaled semiconductor devices.

摘要翻译： 通过在自限制沉积工艺之前或期间提供表面改性方法，可以选择性地改变本身高共形沉积行为，以便在比表面积获得可靠的覆盖，同时显着地减少或抑制不想要的表面积 ，例如高分辨率半导体器件的先进金属化结构中的通孔的底部。

公开(公告)号：US20070278693A1

公开(公告)日：2007-12-06

申请号：US11619235

申请日：2007-01-03

申请人： Matthias Lehr ,  Matthias Schaller ,  Carsten Peters

发明人： Matthias Lehr ,  Matthias Schaller ,  Carsten Peters

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76817 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/7684 ,  H01L23/5283

摘要： A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

摘要翻译： 半导体器件包括在特定金属化层中的金属线，其具有不同的厚度，因此在不同器件区域中具有不同的电阻率。 以这种方式，在装置的高密度区域中，可以提供厚度减小的金属线，以便符合实现相邻金属线之间的最小间距的工艺要求，而在其它区域中，对于最小间距具有较小的关键限制 与常规策略相比，在减小的横向尺寸下可以获得降低的电阻率。 为此，金属化层的电介质材料可以在形成相应的沟槽之前被适当地图案化，或者可以选择性地调整电介质材料的蚀刻行为以获得不同深度的沟槽。

公开(公告)号：US08772154B2

公开(公告)日：2014-07-08

申请号：US13163495

申请日：2011-06-17

申请人： Egon Ronny Pfützner ,  Carsten Peters ,  Jens Heinrich

发明人： Egon Ronny Pfützner ,  Carsten Peters ,  Jens Heinrich

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L23/53295 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.

摘要翻译： 与集成电路的实施例一样，提供了用于制造集成电路的方法的实施例。 在一个实施例中，该方法包括以下步骤：在半导体器件上沉积层间电介质（“ILD”）层，在ILD层上沉积阻挡抛光停止层，以及至少将阻挡抛光停止层和ILD层图案化成 在其中产生多个蚀刻特征。 将铜镀在阻挡抛光停止层上并进入多个蚀刻特征中以产生覆盖阻挡抛光停止层的铜覆盖层和ILD层和阻挡抛光停止层中的多个导电互连特征。 该集成电路被抛光以去除铜覆盖层并暴露阻挡抛光停止层。

公开(公告)号：US07928004B2

公开(公告)日：2011-04-19

申请号：US11671688

申请日：2007-02-06

申请人： Robert Seidel ,  Carsten Peters ,  Frank Feustel

发明人： Robert Seidel ,  Carsten Peters ,  Frank Feustel

IPC分类号： H01L21/4763

CPC分类号： B81B7/0006 ,  B81C2201/0153 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/28114 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76817 ,  H01L21/76838 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2221/1021

摘要： By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.

摘要翻译： 通过基于压印技术形成金属化结构，其中可以通常形成通孔和沟槽，由于根据常规工艺技术所要求的至少一个进一步对准过程，可以实现工艺复杂性的显着降低。 此外，可以通过提供适当设计的压印模具来提高压印光刻的灵活性和效率，以便提供表现出增加的填充能力的通孔开口和沟槽，从而也提高了最终获得的金属化结构在可靠性，抗性 电迁移等。

公开(公告)号：US07902581B2

公开(公告)日：2011-03-08

申请号：US11428611

申请日：2006-07-05

申请人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

发明人： Kai Frohberg ,  Carsten Peters ,  Thomas Werner

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive material such as copper or a copper alloy, a significant increase in conductivity of the contact structure may be achieved. For this purpose, after the deposition of a first dielectric layer of the inter-layer stack, a planarization process may be performed so as to allow the formation of the lower plug portions on the basis of tungsten, while, after the deposition of the second dielectric layer, a corresponding copper-based technology may be used for forming the upper plug portions of significantly enhanced conductivity.

摘要翻译： 通过提供具有基于已经确定的钨基技术形成的下部插塞部分的接触插塞和可包括诸如铜或铜合金的高导电材料的上部插塞部分，导电性的显着增加 可以实现接触结构。 为此，在沉积层间堆叠的第一介电层之后，可以进行平面化处理，以便允许基于钨形成下部塞子部分，而在沉积第二层 电介质层，可以使用相应的铜基技术来形成具有显着增强的导电性的上部插塞部分。

公开(公告)号：US20100285668A1

公开(公告)日：2010-11-11

申请号：US12841313

申请日：2010-07-22

申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

IPC分类号： H01L21/311 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

公开(公告)号：US20090108462A1

公开(公告)日：2009-04-30

申请号：US12104692

申请日：2008-04-17

申请人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

发明人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density.

摘要翻译： 通过在电阻敏感的金属化层中形成延伸穿过整个层间电介质材料的金属线，可获得这些金属化层的均匀性。 相应过孔开口的图案化可以基于形成在盖层中的凹槽来实现，该凹槽在沟槽图案化期间另外充当有效的蚀刻停止层，其延伸穿过整个层间电介质材料。 因此，对于电阻敏感金属化层中金属线的给定设计宽度，可以获得具有高程度均匀性的金属线的最大横截面积，而与通孔密度的变化无关。

公开(公告)号：US07482219B2

公开(公告)日：2009-01-27

申请号：US11424272

申请日：2006-06-15

申请人： Kai Frohberg ,  Carsten Peters ,  Matthias Schaller ,  Heike Salz

发明人： Kai Frohberg ,  Carsten Peters ,  Matthias Schaller ,  Heike Salz

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76831 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides a technique for forming differently stressed contact etch stop layers, wherein sidewall spacers are removed prior to the formation of the contact etch stop layers. During the partial removal of respective contact etch stop layers, a corresponding etch stop layer regime is used to substantially avoid any unwanted stress-inducing material residuals, thereby significantly enhancing the stress transfer mechanism.

摘要翻译： 本发明提供了形成不同应力的接触蚀刻停止层的技术，其中在形成接触蚀刻停止层之前去除侧壁间隔物。 在部分去除相应的接触蚀刻停止层期间，使用相应的蚀刻停止层状态来基本上避免任何不需要的应力诱导材料残余物，从而显着增强应力传递机制。

公开(公告)号：US20110210447A1

公开(公告)日：2011-09-01

申请号：US12939523

申请日：2010-11-04

申请人： Robert Seidel ,  Kai Frohberg ,  Carsten Peters

发明人： Robert Seidel ,  Kai Frohberg ,  Carsten Peters

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76814 ,  H01L21/76829 ,  H01L29/66795 ,  H01L2029/7858

摘要： In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer.

摘要翻译： 在复杂的半导体器件中，可以通过图案化接触开口并以公共沉积顺序用第一金属化层的金属填充接触开口来形成接触电平的接触元件。 为此，在一些说明性实施例中，在沉积第一金属化层的介电材料之前，可以在接触开口中提供牺牲填充材料。

公开(公告)号：US07915170B2

公开(公告)日：2011-03-29

申请号：US11625579

申请日：2007-01-22

申请人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

发明人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

IPC分类号： H01L21/311

CPC分类号： H01L21/76801 ,  H01L21/02087 ,  H01L21/3043 ,  H01L21/31144 ,  H01L21/76802

摘要： By providing a protection layer at the bevel region, the deposition of polymer materials during the patterning process of complex metallization structures may be reduced. Additionally or alternatively, a surface topography may be provided, for instance in the form of respective recesses, in order to enhance the degree of adhesion of any materials deposited in the bevel region during the manufacturing of complex metallization structures. Advantageously, the provision of the protection layer providing the reduced polymer deposition may be combined with the modified surface topography.

摘要翻译： 通过在斜面区域设置保护层，可以减少复杂金属化结构的图形化过程期间聚合物材料的沉积。 附加地或替代地，可以提供例如各自凹部的形式的表面形貌，以便在复杂金属化结构的制造期间增强沉积在斜面区域中的任何材料的粘附程度。 有利的是，提供提供降低的聚合物沉积的保护层可以与改性表面形貌组合。