公开(公告)号：US08772154B2

公开(公告)日：2014-07-08

申请号：US13163495

申请日：2011-06-17

申请人： Egon Ronny Pfützner ,  Carsten Peters ,  Jens Heinrich

发明人： Egon Ronny Pfützner ,  Carsten Peters ,  Jens Heinrich

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L23/53295 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.

摘要翻译： 与集成电路的实施例一样，提供了用于制造集成电路的方法的实施例。 在一个实施例中，该方法包括以下步骤：在半导体器件上沉积层间电介质（“ILD”）层，在ILD层上沉积阻挡抛光停止层，以及至少将阻挡抛光停止层和ILD层图案化成 在其中产生多个蚀刻特征。 将铜镀在阻挡抛光停止层上并进入多个蚀刻特征中以产生覆盖阻挡抛光停止层的铜覆盖层和ILD层和阻挡抛光停止层中的多个导电互连特征。 该集成电路被抛光以去除铜覆盖层并暴露阻挡抛光停止层。

公开(公告)号：US08580684B2

公开(公告)日：2013-11-12

申请号：US12939523

申请日：2010-11-04

申请人： Robert Seidel ,  Kai Frohberg ,  Carsten Peters

发明人： Robert Seidel ,  Kai Frohberg ,  Carsten Peters

IPC分类号： H01L21/44

CPC分类号： H01L21/76808 ,  H01L21/76814 ,  H01L21/76829 ,  H01L29/66795 ,  H01L2029/7858

摘要： In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer.

摘要翻译： 在复杂的半导体器件中，可以通过图案化接触开口并以公共沉积顺序用第一金属化层的金属填充接触开口来形成接触电平的接触元件。 为此，在一些说明性实施例中，在沉积第一金属化层的介电材料之前，可以在接触开口中提供牺牲填充材料。

公开(公告)号：US07998823B2

公开(公告)日：2011-08-16

申请号：US11533793

申请日：2006-09-21

申请人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

发明人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

IPC分类号： H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/76897 ,  H01L21/823475

摘要： By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

摘要翻译： 通过在接触区域可以连接到漏极和源极区域的区域处形成具有增加的结深度的附加掺杂区域，可以将任何接触不规则物嵌入到附加掺杂区域中，从而降低漏极和漏极之间的漏电流或短路的风险 源极区域和通常由接触不规则引起的阱区域。 此外，附加地或替代地，可以在形成金属硅化物区域和接触插塞之前修改半导体区域和相邻隔离沟槽的表面形貌，以增强在层间电介质材料中形成相应接触开口的光刻过程。 为此，与相邻的半导体区域相比，隔离沟槽可以达到相同或更高的水平。

公开(公告)号：US07875514B2

公开(公告)日：2011-01-25

申请号：US12841313

申请日：2010-07-22

申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

公开(公告)号：US07678690B2

公开(公告)日：2010-03-16

申请号：US11534285

申请日：2006-09-22

申请人： Ralf Richter ,  Carsten Peters ,  Heike Salz ,  Matthias Schaller

发明人： Ralf Richter ,  Carsten Peters ,  Heike Salz ,  Matthias Schaller

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： By providing additional etch stop layers and/or etch protection layers, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. Consequently, conductive line erosion and/or penetration into extension regions may be significantly reduced, thereby improving the reliability and performance of corresponding semiconductor devices.

摘要翻译： 通过提供附加的蚀刻停止层和/或蚀刻保护层，可以以高度可靠的方式控制用于形成用于直接连接多晶硅线路和有源区域的接触开口的相应蚀刻工艺。 因此，可以显着地减少导线侵蚀和/或穿透到延伸区域，从而提高对应的半导体器件的可靠性和性能。

公开(公告)号：US20090085030A1

公开(公告)日：2009-04-02

申请号：US12056362

申请日：2008-03-27

申请人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

发明人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

IPC分类号： H01L29/06 ,  H01L21/44 ,  H01L29/78

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

摘要翻译： 通过形成直接接触结构，例如通过在硅化处理之前去除侧壁间隔物，在增加量的金属硅化物的基础上连接有源区域，可以在接触期间实现显着增加的蚀刻选择性 蚀刻停止层开口。 因此，有效区域的高掺杂硅材料的过度蚀刻将被抑制。 附加地或替代地，公开了适当设计的测试结构，其可以检测根据特定制造顺序形成的接触结构的电特性，并且可以基于特定的设计标准。

公开(公告)号：US20080003830A1

公开(公告)日：2008-01-03

申请号：US11625579

申请日：2007-01-22

申请人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

发明人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

IPC分类号： H01L21/311

CPC分类号： H01L21/76801 ,  H01L21/02087 ,  H01L21/3043 ,  H01L21/31144 ,  H01L21/76802

摘要： By providing a protection layer at the bevel region, the deposition of polymer materials during the patterning process of complex metallization structures may be reduced. Additionally or alternatively, a surface topography may be provided, for instance in the form of respective recesses, in order to enhance the degree of adhesion of any materials deposited in the bevel region during the manufacturing of complex metallization structures. Advantageously, the provision of the protection layer providing the reduced polymer deposition may be combined with the modified surface topography.

摘要翻译： 通过在斜面区域设置保护层，可以减少复杂金属化结构的图形化过程期间聚合物材料的沉积。 附加地或替代地，可以提供例如各自凹部的形式的表面形貌，以便在复杂金属化结构的制造期间增强沉积在斜面区域中的任何材料的粘附程度。 有利的是，提供提供降低的聚合物沉积的保护层可以与改性表面形貌组合。

公开(公告)号：US20070178691A1

公开(公告)日：2007-08-02

申请号：US11536730

申请日：2006-09-29

申请人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

发明人： Ralf Richter ,  Carsten Peters ,  Holger Schuehrer

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  H01L21/7684 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

摘要翻译： 通过提供大面积金属板与相应的周边区域结合增加的粘合特性，可以有效地监测分层事件，而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中，可以在大面积金属板的周边设置虚拟通孔，从而允许中心区域分层，同时基本避免金属板的完全分层。 因此，可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。

公开(公告)号：US20070178685A1

公开(公告)日：2007-08-02

申请号：US11538111

申请日：2006-10-03

申请人： Carsten Peters ,  Heike Salz ,  Ralf Richter ,  Matthias Schaller

发明人： Carsten Peters ,  Heike Salz ,  Ralf Richter ,  Matthias Schaller

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/665

摘要： By providing an additional silicon dioxide based etch stop layer, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. In another aspect, the etch selectivity of the contact structure may be increased by a modification of the etch behavior of the exposed portion of the contact etch stop layer.

摘要翻译： 通过提供另外的基于二氧化硅的蚀刻停止层，可以以高度可靠的方式控制用于形成用于直接连接多晶硅线和有源区的接触开口的相应蚀刻工艺。 在另一方面，可以通过接触蚀刻停止层的暴露部分的蚀刻行为的修改来增加接触结构的蚀刻选择性。

公开(公告)号：US20070161225A1

公开(公告)日：2007-07-12

申请号：US11533793

申请日：2006-09-21

申请人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

发明人： Carsten Peters ,  Kai Frohberg ,  Ralf Richter

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823481 ,  H01L21/76897 ,  H01L21/823475

摘要： By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

摘要翻译： 通过在接触区域可以连接到漏极和源极区域的区域处形成具有增加的结深度的附加掺杂区域，可以将任何接触不规则物嵌入到附加掺杂区域中，从而降低漏极和漏极之间的漏电流或短路的风险 源极区域和通常由接触不规则引起的阱区域。 此外，附加地或替代地，可以在形成金属硅化物区域和接触插塞之前修改半导体区域和相邻隔离沟槽的表面形貌，以增强在层间电介质材料中形成相应接触开口的光刻过程。 为此，与相邻的半导体区域相比，隔离沟槽可以达到相同或更高的水平。