公开(公告)号：US20140266114A1

公开(公告)日：2014-09-18

申请号：US14291426

申请日：2014-05-30

申请人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

发明人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC分类号： H02M3/158

CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

摘要： A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

摘要翻译： 电压调节器电路包括具有反相输入和非反相输入的放大器。 放大器被配置为基于放大器的反相输入端处的参考信号和放大器的非反相输入端的反馈信号产生控制信号。 电压调节器电路还包括响应于控制信号产生朝向输出节点流动的驱动电流的输出节点，第一功率节点，第二功率节点和驱动器。 驱动器耦合在第一功率节点和输出节点之间。 具有栅极的第一晶体管耦合在输出节点和第二功率节点之间。 放大器外部的偏置电路向第一晶体管的栅极提供偏置信号，该偏置信号被配置为基于偏置电路提供的偏置信号在饱和模式下工作。

公开(公告)号：US20140015582A1

公开(公告)日：2014-01-16

申请号：US13547396

申请日：2012-07-12

申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Derek C. TAO

发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Derek C. TAO

IPC分类号： H03K3/356

CPC分类号： H03K5/08 ,  H03K3/356139 ,  H04L27/01

摘要： This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

摘要翻译： 该描述涉及包括第一锁存器的限幅器。 第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。 第一时钟信号与第二时钟信号不同。 第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。 第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。 第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。 切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。 切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

公开(公告)号：US20130346811A1

公开(公告)日：2013-12-26

申请号：US13528877

申请日：2012-06-21

申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Yuwen SWEI ,  Chih-Chang LIN ,  Tsung-Ching HUANG

IPC分类号： G06F1/04 ,  G06F11/00

CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

公开(公告)号：US20130141170A1

公开(公告)日：2013-06-06

申请号：US13312228

申请日：2011-12-06

申请人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

发明人： Tao Wen CHUNG ,  Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC分类号： H03F3/68

CPC分类号： H03F3/68 ,  H03F1/42 ,  H03F3/191 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/36 ,  H03F2200/405 ,  H03F2203/45638 ,  H03F2203/45702

摘要： A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

摘要翻译： 共享用于具有至少两级的放大器的感应峰化的电感器的方法包括计算用于感应峰值的至少两级的单级的单级电感，以便具有稳定的脉冲响应。 通过将单级电感除以至少两级的多个级来计算感应峰值的共享电感。 具有共享电感的至少两个电感器在用于感应峰化的至少两个级中共享。

公开(公告)号：US20120223752A1

公开(公告)日：2012-09-06

申请号：US13039095

申请日：2011-03-02

申请人： Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tao Wen CHUNG ,  Chan-Hong CHERN

发明人： Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tao Wen CHUNG ,  Chan-Hong CHERN

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/089 ,  H03L7/0893

摘要： A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.

摘要翻译： 锁相环（PLL）包括配置成提供输出信号的压控振荡器（VCO）。 相位频率检测器（PFD）被配置为接收参考频率信号并提供第一控制信号。 第一电荷泵被配置为接收第一控制信号并提供第一电压信号以便控制VCO。 第二电荷泵被配置为接收第一控制信号并提供第二电压信号。 比较器被配置为接收参考电压信号，以比较参考电压信号和第二电压信号，并提供第二控制信号。 PFD被配置为基于第二控制信号来调整第一控制信号的至少一个侧斜率。

公开(公告)号：US20120200323A1

公开(公告)日：2012-08-09

申请号：US13448878

申请日：2012-04-17

申请人： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

发明人： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/081 ,  H03L7/087

摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

摘要翻译： 包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于 输入信号。 电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是 晚于输入信号。 电路还包括被配置为产生第一增加信号的第三电路。 电路还包括被配置为产生第一减小信号的第四电路。

公开(公告)号：US20100253303A1

公开(公告)日：2010-10-07

申请号：US12750260

申请日：2010-03-30

申请人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

发明人： Chan-Hong CHERN ,  Tzu Ching CHANG ,  Min-Shueh YUAN ,  Yuwen SWEI ,  Chih-Chang LIN ,  Chiang PU ,  Ming-Chieh HUANG ,  Kuoyuan HSU

IPC分类号： G05F1/10

CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

摘要翻译： 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

公开(公告)号：US20130120051A1

公开(公告)日：2013-05-16

申请号：US13737624

申请日：2013-01-09

申请人： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

发明人： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

IPC分类号： G05F1/10

CPC分类号： G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

摘要： A circuit includes a comparator, a first circuit, and a second circuit. The comparator includes a first input node, a second input node, and an output node. The first circuit is configured to generate a temperature-dependent reference current at the second input node of the comparator. The second circuit is coupled with the second input node of the comparator. The second circuit is configured to increase a voltage level at the second input node of the comparator in response to the temperature-dependent reference current when a signal at the output node of the comparator indicates a first comparison result, and decrease the voltage level at the second input node of the comparator when the signal at the output node of the comparator indicates a second comparison result.

摘要翻译： 电路包括比较器，第一电路和第二电路。 比较器包括第一输入节点，第二输入节点和输出节点。 第一电路被配置为在比较器的第二输入节点处产生与温度相关的参考电流。 第二电路与比较器的第二输入节点耦合。 第二电路被配置为当比较器的输出节点处的信号指示第一比较结果时，响应于温度相关的参考电流来增加比较器的第二输入节点处的电压电平，并且降低电压电平 当比较器的输出节点处的信号指示第二比较结果时，比较器的第二输入节点。

公开(公告)号：US20120026820A1

公开(公告)日：2012-02-02

申请号：US12844204

申请日：2010-07-27

申请人： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

发明人： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

IPC分类号： G11C7/00 ,  G05F1/10

CPC分类号： G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

摘要： An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.

摘要翻译： 集成电路包括电容器。 开关以并联方式与电容器电耦合。 比较器包括第一输入节点，第二输入节点和输出节点。 第二输入节点与电容器的第一板电耦合。 输出节点与开关电耦合。 晶体管与电容器的第二板电耦合。 电路与晶体管的栅极电耦合。 电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

公开(公告)号：US20120032518A1

公开(公告)日：2012-02-09

申请号：US12851023

申请日：2010-08-05

申请人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  David Barry SCOTT

发明人： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  David Barry SCOTT

IPC分类号： H02J1/10

CPC分类号： H02J7/35 ,  H02J1/10 ,  H02J7/0055 ,  H02J7/025 ,  H02J17/00 ,  H02J50/00 ,  H02J50/20 ,  H02J50/30 ,  H02J50/40 ,  Y10T307/702

摘要： An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.

摘要翻译： 能量收集系统包括多个换能器。 传感器被配置为从多个环境能量源产生直流（DC）电压。 传感器控制电路具有被配置为检测来自多个换能器的直流信号的多个传感器。 DC-DC转换器被配置为提供输出电压。 多个开关，每个开关耦合在DC-DC转换器和多个换能器中的相应换能器之间。 传感器控制电路使得多个开关中的一个开关能够基于优先级标准而禁用多个开关中的其它开关。