公开(公告)号：US20060253661A1

公开(公告)日：2006-11-09

申请号：US11120909

申请日：2005-05-03

申请人： Brian Bass ,  Thomas Jeremiah ,  Charles Johns ,  David Shippy ,  Thuong Truong

发明人： Brian Bass ,  Thomas Jeremiah ,  Charles Johns ,  David Shippy ,  Thuong Truong

IPC分类号： G06F13/00 ,  G06F12/06

CPC分类号： G06F12/06

摘要： The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.

公开(公告)号：US20080040549A1

公开(公告)日：2008-02-14

申请号：US11875407

申请日：2007-10-19

申请人： Michael Day ,  Charles Johns ,  Thuong Truong

发明人： Michael Day ,  Charles Johns ,  Thuong Truong

IPC分类号： G06F12/08 ,  G06F12/14

CPC分类号： G06F12/0848 ,  G06F12/0875

摘要： The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

摘要翻译： 本发明提供一种将从I / O设备，网络或盘传送的数据存储到高速缓存或其他快速存储器的一部分中的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。 在本发明的一个实施例中，处理器可以将数据写入高速缓存或其它快速存储器，而不将其写入主存储器。 高速缓存或其他快速存储器的部分可以用作额外的系统存储器。

公开(公告)号：US20080040548A1

公开(公告)日：2008-02-14

申请号：US11874513

申请日：2007-10-18

申请人： Michael Day ,  Charles Johns ,  Thuong Truong

发明人： Michael Day ,  Charles Johns ,  Thuong Truong

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F12/0848 ,  G06F2212/2515

摘要： The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

摘要翻译： 本发明提供了一种用于处理器将数据写入高速缓存或其他快速存储器的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。 锁定缓存或其他快速存储器可用作附加系统内存。 在本发明的实施例中，锁定高速缓存是多组关联高速缓存的一组或多组方式，但不是所有的集合或方式。

公开(公告)号：US20060095669A1

公开(公告)日：2006-05-04

申请号：US10976263

申请日：2004-10-28

申请人： Michael Day ,  Charles Johns ,  Thuong Truong

发明人： Michael Day ,  Charles Johns ,  Thuong Truong

IPC分类号： G06F12/14

CPC分类号： G06F12/0848 ,  G06F12/0875

摘要： The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

摘要翻译： 本发明提供一种将从I / O设备，网络或盘传送的数据存储到高速缓存或其他快速存储器的一部分中的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。 在本发明的一个实施例中，处理器可以将数据写入高速缓存或其它快速存储器，而不将其写入主存储器。 高速缓存或其他快速存储器的部分可以用作额外的系统存储器。

公开(公告)号：US20070162640A1

公开(公告)日：2007-07-12

申请号：US11291735

申请日：2005-12-01

申请人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

发明人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

摘要翻译： 公开了用于有效地切换处理元件之间的上下文的系统和方法。 这些系统和方法可将处理元件的上下文传送到存储位置。 使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。 然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

公开(公告)号：US07590774B2

公开(公告)日：2009-09-15

申请号：US11291735

申请日：2005-12-01

申请人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

发明人： Charles Johns ,  Peichun Liu ,  Takashi Omizo

IPC分类号： G06F13/28 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F13/28

摘要： Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

摘要翻译： 公开了用于有效地切换处理元件之间的上下文的系统和方法。 这些系统和方法可以将处理元件的上下文传送到存储位置。 使用目标处理元件的DMA控制器，该存储位置的内容可以被传送到与目标处理元件相关联的另一存储位置。 然后，该上下文可以从该存储位置恢复到目标处理元件中的适当位置，并且目标处理元件然后可以利用该传送的上下文开始处理。

公开(公告)号：US20060265546A1

公开(公告)日：2006-11-23

申请号：US11130911

申请日：2005-05-17

申请人： Paul Ganfield ,  Kent Haselhorst ,  Charles Johns ,  Peichun Liu

发明人： Paul Ganfield ,  Kent Haselhorst ,  Charles Johns ,  Peichun Liu

IPC分类号： G06F12/00

CPC分类号： G11C7/1006

摘要： A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

摘要翻译： 提供了一种用于处理XDR DRAM存储器系统中的写掩码操作的方法，装置和计算机程序产品。 本发明消除了对双端口阵列的需要，因为在接收到数据时完成了掩码生成。 掩码计算需要较少的逻辑，因为256个可能的字节值中只有144个被解码。 掩码值生成并存储在掩码数组中。 独立地，写入数据被存储在写入缓冲器中。 掩码值用于生成写掩码命令。 一旦写掩码命令被发出，写入数据和掩码值被发送到多路复用器。 多路器使用掩码值对写入数据进行掩码，以便将掩蔽的数据存储在XDR DRAMS中。

公开(公告)号：US20050111354A1

公开(公告)日：2005-05-26

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/24 ,  H04L12/26

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20070283103A1

公开(公告)日：2007-12-06

申请号：US11840284

申请日：2007-08-17

申请人： Harm Hofstee ,  Charles Johns ,  James Kahle

发明人： Harm Hofstee ,  Charles Johns ,  James Kahle

IPC分类号： G06F12/00

CPC分类号： G06F12/0284 ,  G06F13/1652

摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

摘要翻译： 提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。 公共总线用于将公共存储器耦合到各种处理器。 在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。 在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。 在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

公开(公告)号：US20070168538A1

公开(公告)日：2007-07-19

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.