Semiconductor package with heat sink
    21.
    发明申请
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号:US20060017145A1

    公开(公告)日:2006-01-26

    申请号:US11212182

    申请日:2005-08-26

    Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

    Abstract translation: 提供了具有散热器的半导体封装,其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔,允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此,不需要在基板上形成预定的孔,用于连接诸如螺栓的固定构件,并且散热器的结合不会影响迹线布线性以及诸如衬底上的焊球等输入/输出连接的布置 不会导致芯片的裂纹。

    Chip carrier for semiconductor chip
    22.
    发明申请
    Chip carrier for semiconductor chip 有权
    半导体芯片芯片载体

    公开(公告)号:US20050040524A1

    公开(公告)日:2005-02-24

    申请号:US10909029

    申请日:2004-07-30

    Abstract: A chip carrier for a semiconductor chip is provided. A plurality of solder pads for bump soldering are formed on a chip mounting surface of the chip carrier, to allow a flip chip to be mounted and electrically connected to the chip carrier. A solder mask layer is formed on the chip carrier, wherein a plurality of openings are provided in the solder mask layer to expose the solder pads, and an outwardly opening extended portion is formed respectively from the openings corresponding to the solder pads having a relatively narrower pitch therebetween, so as to prevent formation of voids during an underfill process for filing a gap between the flip chip and the chip carrier.

    Abstract translation: 提供了一种用于半导体芯片的芯片载体。 在芯片载体的芯片安装表面上形成用于凸块焊接的多个焊盘,以允许倒装芯片安装并电连接到芯片载体。 在芯片载体上形成焊料掩模层,其中在焊料掩模层中设置多个开口以露出焊盘,并且从对应于具有相对较窄的焊盘的开口分别形成向外开口的延伸部分 间隔,以防止在底部填充过程中形成空隙,以便在倒装芯片和芯片载体之间填充间隙。

    Method and apparatus for transmitting registered data onto a PCI bus
    23.
    发明授权
    Method and apparatus for transmitting registered data onto a PCI bus 有权
    将注册数据发送到PCI总线上的方法和装置

    公开(公告)号:US06578097B1

    公开(公告)日:2003-06-10

    申请号:US09651423

    申请日:2000-08-30

    CPC classification number: G06F13/423 G06F13/4068

    Abstract: A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity. The apparatus employee a 2R1W data buffer to send a current phase data and a next phase data one clock cycle ahead of the actual AD activity on PCI bus and use a multiplexer to select the current phase data or the next phase data according to a select signal. The select signal is outputted by a OR gate with IRDY# and TRDY# signals as its inputs. Then, the apparatus use a flip-flop to toggling the output signal of the multiplexer to the PCI bus at the actual AD activity. Therefore, the apparatus of the present invention not only reduce the delay time of manipulating the outgoing signals, but also is implemented with simple architecture.

    Abstract translation: 提供一种将注册数据发送到PCI总线上的方法和装置,其可以减少操纵输出信号的延迟时间,而不会大大增加电路复杂度。 该设备雇员一个2R1W数据缓冲器,用于在PCI总线上的实际AD活动之前一个时钟周期发送当前相位数据和下一个相位数据,并使用多路复用器根据选择信号选择当前相位数据或下一个相位数据 。 选择信号由IRDY#和TRDY#信号作为其输入的或门输出。 然后,该设备使用触发器在实际的AD活动下切换多路复用器的输出信号到PCI总线。 因此,本发明的装置不仅减少了操纵输出信号的延迟时间,而且还以简单的架构来实现。

    Processing modules with multilevel cache architecture
    24.
    发明授权
    Processing modules with multilevel cache architecture 有权
    处理具有多级缓存架构的模块

    公开(公告)号:US07596661B2

    公开(公告)日:2009-09-29

    申请号:US11307073

    申请日:2006-01-23

    CPC classification number: G06F12/0848 G06F12/0857 G06F12/0897

    Abstract: A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.

    Abstract translation: 具有多级缓存架构的处理模块,包括:处理器; 耦合到所述处理器的用于缓存所述处理器的数据的一级(L1)高速缓存,其中所述L1高速缓存具有至少一个L1可高速缓存的范围; 耦合到L1高速缓存用于缓存处理器的数据的二级(L2)高速缓存,其中所述L2高速缓存具有至少一个L2可高速缓存的范围,并且所述L1高速缓存范围和所述L2高速缓存范围是相互排斥的; 以及耦合到L1高速缓存和L2高速缓存的存储器接口,用于在L1高速缓存和存储器之间传送数据并用于在L2高速缓存和存储器之间传送数据。

    GENERAL PURPOSE INTERFACE CONTROLLER OF RESOURE LIMITED SYSTEM
    25.
    发明申请
    GENERAL PURPOSE INTERFACE CONTROLLER OF RESOURE LIMITED SYSTEM 有权
    一般用途接口控制器

    公开(公告)号:US20090182921A1

    公开(公告)日:2009-07-16

    申请号:US12271073

    申请日:2008-11-14

    CPC classification number: G06F13/387

    Abstract: The invention discloses a general purpose interface controller, including a slave interface controller and a master interface controller, used to exchange data among master devices and slave devices in an electronic device. The slave interface controller receives data and a first control signal from one of the master devices, and converts the first control signal to a request signal. The master interface controller receives the data and the request signal from the slave interface controller, converts the request signal to a second control signal recognized by at least one of the slave devices, and forwards the data and the second control signal to the slave device.

    Abstract translation: 本发明公开了一种通用接口控制器,包括从接口控制器和主接口控制器,用于在电子设备中的主设备和从设备之间交换数据。 从接口控制器从主设备之一接收数据和第一控制信号,并将第一控制信号转换为请求信号。 主接口控制器从从接口控制器接收数据和请求信号,将请求信号转换成由至少一个从设备识别的第二控制信号,并将数据和第二控制信号转发给从设备。

    Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems
    26.
    发明授权
    Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems 有权
    具有指令预取设备的嵌入式系统,以及用于在嵌入式系统中取指令的方法

    公开(公告)号:US07234041B2

    公开(公告)日:2007-06-19

    申请号:US10458470

    申请日:2003-06-10

    Applicant: Chang-Fu Lin

    Inventor: Chang-Fu Lin

    CPC classification number: G06F9/3802 G06F9/3808

    Abstract: In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetch device is also disclosed.

    Abstract translation: 在用于在嵌入式系统中取指令的方法中,当系统总线处于数据访问阶段时,存储在存储器件中的一组指令中的预测的一个指令被取出并随后被存储在指令缓冲器中。 当处理器产生对存储器件的访问请求时,存储在指令缓冲器中的指令中的预测的一个指令被提供给系统总线,以便在确定存储在指令缓冲器中的预测指令之一被命中时被处理器接收 来自处理器的访问请求。 还公开了一种具有指令预取装置的嵌入式系统。

    Semiconductor package with heat sink
    27.
    发明申请
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号:US20050280132A1

    公开(公告)日:2005-12-22

    申请号:US11212290

    申请日:2005-08-26

    Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

    Abstract translation: 提供了具有散热器的半导体封装,其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔,允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此,不需要在基板上形成预定的孔,用于连接诸如螺栓的固定构件,并且散热器的结合不会影响迹线布线性以及诸如衬底上的焊球等输入/输出连接的布置 不会导致芯片的裂纹。

    Flip-chip semiconductor package and package substrate applicable thereto
    28.
    发明申请
    Flip-chip semiconductor package and package substrate applicable thereto 审中-公开
    倒装芯片半导体封装和适用于其的封装基板

    公开(公告)号:US20080277802A1

    公开(公告)日:2008-11-13

    申请号:US12151904

    申请日:2008-05-08

    Abstract: A flip-chip semiconductor package structure and a package substrate applicable thereto are disclosed. The package substrate includes a body having at least a chip-attach area disposed thereon; a plurality of solder pads disposed in the chip-attach area and arranged at different intervals; and a fluid-disturbing portion disposed in the chip-attach area at a position where the solder pads are loosely arranged. A flip-chip semiconductor chip is mounted on the solder pads via conductive bumps and an underfill material is filled between the package substrate and the flip-chip semiconductor chip, the underfill material encapsulating the conductive bumps and the fluid-disturbing portion. By protrudingly disposing the fluid-disturbing portion at a position where the conductive bumps are loosely arranged, that is, the conductive bumps having bigger intervals therebetween, gap between the package substrate and the flip-chip semiconductor chip can be reduced so as to increase capillary attraction generated by capillary phenomenon, thereby balancing flow rate of the underfill material between the conductive bumps that are arranged at different intervals and thus avoiding problems of void formation, subsequent popcorn effect or delamination as encountered in the prior art.

    Abstract translation: 公开了一种倒装芯片半导体封装结构和可应用于其的封装衬底。 封装基板包括:至少设置有芯片附着区域的主体; 多个焊盘,设置在芯片附着区域中并以不同的间隔布置; 以及布置在所述芯片附着区域中的焊料松散布置的位置处的流体干扰部分。 通过导电凸块将倒装芯片半导体芯片安装在焊盘上,并且在封装衬底和倒装芯片半导体芯片之间填充底部填充材料,封装有导电凸块和流体干扰部分的底部填充材料。 通过将导体凸块松动配置的位置突出地配置,即,导电性凸起间隔较大的间隙,可以减小封装基板与倒装芯片半导体芯片之间的间隙,从而增加毛细管 由毛细管现象产生的吸引力,从而平衡以不同间隔布置的导电凸块之间的底部填充材料的流速,从而避免了现有技术中遇到的空隙形成问题,随后的爆米花效应或分层现象。

    Semiconductor package with heat sink
    30.
    发明授权
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号:US07177155B2

    公开(公告)日:2007-02-13

    申请号:US11212290

    申请日:2005-08-26

    Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

    Abstract translation: 提供了具有散热器的半导体封装,其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔,允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此,不需要在基板上形成预定的孔,用于连接诸如螺栓的固定构件,并且散热器的结合不会影响迹线布线性以及衬底上的诸如焊球的输入/输出连接的布置 不会导致芯片的裂纹。

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