公开(公告)号：US6069044A

公开(公告)日：2000-05-30

申请号：US291270

申请日：1999-04-14

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L21/2652 ,  H01L21/28123 ,  H01L29/6653 ,  H01L29/6659 ,  H01L21/2236 ,  H01L21/2255 ,  H01L29/665 ,  H01L29/66545

Abstract: The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A photoresist layer is formed over the first dielectric layer. Next, the photoresist layer is patterned to define a gate region. An etching process is performed to the photoresist layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual photoresist layer as a mask. The undoped polysilicon layer is etched by using the residual photoresist layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate. Next, a high dose arsenic or phosphorus ion implantation is performed through the metal layer to form first doped regions to serve as source and drain regions of the transistor. Finally, the two-step RTP annealing process is used to form self-aligned silicided contact of nMOSFETs.

Abstract translation: 本发明的方法包括以下步骤。 首先，在基板上形成栅氧化层。 在栅极氧化物层上形成未掺杂的多晶硅层。 然后，在未掺杂的多晶硅层上形成第一介电层。 在第一电介质层上形成光致抗蚀剂层。 接下来，对光致抗蚀剂层进行图案化以限定栅极区域。 对光致抗蚀剂层进行蚀刻处理以使栅极区域变窄。 通过使用残留光致抗蚀剂层作为掩模来蚀刻第一介电层的一部分。 通过使用残留光致抗蚀剂层和残留的第一介电层作为掩模来蚀刻未掺杂的多晶硅层。 然后，在剩余的第一介电层和基板上沉积PSG层。 随后，将PSG层回蚀以形成侧壁间隔物以用作离子扩散源。 在基板的所有区域上沉积高贵或难熔金属层。 接下来，通过金属层进行高剂量砷或磷离子注入，以形成用作晶体管的源极和漏极区的第一掺杂区域。 最后，使用两步RTP退火工艺来形成nMOSFET的自对准硅化物接触。

公开(公告)号：US6057195A

公开(公告)日：2000-05-02

申请号：US83609

申请日：1998-05-22

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8246

CPC classification number: H01L27/1126

Abstract: A method of fabricating high-density flat cell mask ROM is disclosed. The method comprises, formed a plurality of trenches in a silicon substrate firstly. An oxynitride layer is then grown on resultant surfaces to about 1-5 nm, After refilling a plurality of trenches with a first in-situ phosphorus doping polysilicon layer or amorphous silicon, etching back the polysilicon layer to form a flat surface by a CMP process is achieved. Subsequently, a thermal oxidation process is carried out to grow an oxide layer and to form a plurality of buried bit lines by diffusing the conductive impurities in the polysilicon layer through the oxynitride layer into the silicon substrate. A second in-situ n+ doped polysilicon layer is deposited and patterned as word lines; then a patterned photoresist coated on the second polysilicon layer except predetermining coding regions. Finally, a coding boron implant into the predetermined coding region is done to form normally off transistors.

Abstract translation: 公开了一种制造高密度扁平单元掩膜ROM的方法。 该方法首先在硅衬底中形成多个沟槽。 然后在所得表面上生长氮氧化物层至约1-5nm。在用第一原位磷掺杂多晶硅层或非晶硅再填充多个沟槽之后，通过CMP工艺蚀刻多晶硅层以形成平坦表面 已完成。 随后，通过将多晶硅层中的导电杂质通过氧氮化物层扩散到硅衬底中，进行热氧化处理以生长氧化物层并形成多个掩埋位线。 第二原位n +掺杂多晶硅层被沉积并图案化为字线; 然后涂覆在第二多晶硅层上的图案化光致抗蚀剂，除了预先确定编码区域。 最后，进行到预定编码区域中的编码硼注入以形成常闭晶体管。

公开(公告)号：US6043124A

公开(公告)日：2000-03-28

申请号：US42347

申请日：1998-03-13

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336

CPC classification number: H01L21/28273

Abstract: The present invention proposes a method for fabricating a high speed and high density nonvolatile memory cell. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited on the substrate and then the tunnel oxide region is defined by a standard photolithography process followed by an anisotropic etching. A high temperature steam oxidation process is used to grow a thick thermal oxide on the non-tunnel region. After removing the masking silicon nitride layer, the n+ impurity ions is implanted to form the source and drain, and a thermal annealing is performed to recover the implantation damage and to drive in the doped ions. Next, the pad oxide film is etched back and an ultra-thin undoped .alpha.-Si, or HSG-Si, film is deposited. A thermal oxidation process is carried out to convert the undoped .alpha.-Si or HSG-Si into textured tunnel oxide. Finally, the first n+ doped polysilicon film which serves as the floating gate, the interpoly dielectric such as ONO, the second n+ doped polysilicon film which serves as the control gate are sequentially formed, and the memory cell is finished.

Abstract translation: 本发明提出一种制造高速和高密度非易失性存储单元的方法。 首先，制备具有限定的场氧化物和有源区的半导体衬底。 堆叠的氧化硅/氮化硅层沉积在衬底上，然后通过标准光刻工艺定义隧道氧化物区域，随后进行各向异性蚀刻。 使用高温蒸汽氧化工艺在非隧道区域上生长厚的热氧化物。 在去除掩模氮化硅层之后，注入n +杂质离子以形成源极和漏极，并进行热退火以恢复注入损伤并驱动掺杂离子。 接下来，将衬垫氧化膜回蚀刻，并沉积超薄的未掺杂的α-Si或HSG-Si膜。 进行热氧化处理以将未掺杂的α-Si或HSG-Si转化成纹理化的隧道氧化物。 最后，依次形成用作浮置栅极的第一n +掺杂多晶硅膜，作为控制栅极的第二n +掺杂多晶硅膜，诸如ONO的多晶硅电介质，并且存储单元被完成。

公开(公告)号：US6027981A

公开(公告)日：2000-02-22

申请号：US958536

申请日：1997-10-27

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for forming a fork-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first doped polysilicon layer (118) over a semiconductor substrate (110), wherein at least a portion of the first doped polysilicon layer communicates to the substrate. A first dielectric layer (119) is formed on the first doped polysiliocn layer, and is then patterned to define a storage node therein. Next, a second doped polysilicon layer (122) is formed on the first dielectric layer and the first doped polysilicon layer, and a second dielectric spacer (124) is formed on a sidewall of the second doped polysilicon layer. After etching the second doped polysilicon layer and the first doped polysilicon layer using the second dielectric spacer as a mask to expose surface of the first dielectric layer, a third doped polysiliocn spacer (126) is formed on a sidewall of the second dielectric spacer. The second dielectric spacer and the first dielectric layer are then removed, and a fourth dielectric layer (136) is formed on the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysiliocn spacer. Finally, a conductive layer (138) is formed on the fourth dielectric layer.

Abstract translation: 公开了一种用于形成动态随机存取存储器单元的叉形电容器的方法。 该方法包括在半导体衬底（110）上形成第一掺杂多晶硅层（118），其中第一掺杂多晶硅层的至少一部分与衬底通信。 第一介电层（119）形成在第一掺杂多晶硅层上，然后被图案化以在其中限定存储节点。 接下来，在第一介电层和第一掺杂多晶硅层上形成第二掺杂多晶硅层（122），在第二掺杂多晶硅层的侧壁上形成第二介电隔离物（124）。 在使用第二介电间隔物作为掩模蚀刻第二掺杂多晶硅层和第一掺杂多晶硅层以暴露第一介电层的表面之后，在第二介电间隔物的侧壁上形成第三掺杂聚硅氧烷间隔物（126）。 然后去除第二电介质隔离物和第一介电层，并且在第一掺杂多晶硅层，第二掺杂多晶硅层和第三掺杂聚硅氧烷间隔物上形成第四介电层（136）。 最后，在第四电介质层上形成导电层（138）。

公开(公告)号：US6008079A

公开(公告)日：1999-12-28

申请号：US48549

申请日：1998-03-25

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8247 ,  H01L21/338 ,  H01L21/8242

CPC classification number: H01L27/11521

Abstract: The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist. An anisotropic etching follows to etch the silicon layer and then the n+ impurity ions are implanted to form the source and drain. After stripping the photoresist, a high temperature steam oxidation process is used to grow a thick field oxide, and the doped ions are active and driven in to form the buried bit lines simultaneously. The silicon nitride layer and the pad oxide layer are then removed, and the silicon substrate is recessed by using the field oxide as an etching mask. After rounding the trench corners by using thermal oxidation and etching back processes, a thin silicon oxy-nitride film is regrown. An in-situ doped polysilicon film is deposited to refill the trench region and then etch back by using a CMP process to form the floating gates. Next, the interpoly dielectric such as ultra-thin ONO film, and, the control gate formed of n+ doped polysilicon film, are sequentially built. After the word lines are defined, the nonvolatile memory is thus finished.

Abstract translation: 本发明提出了一种制造高密度浅沟槽非接触非易失性存储器的方法。 首先，在衬底上沉积堆叠的衬垫氧化物/氮化硅层，并且掩模位线区域由光致抗蚀剂限定。 随后进行各向异性蚀刻以蚀刻硅层，然后注入n +杂质离子以形成源极和漏极。 在剥离光致抗蚀剂之后，使用高温蒸汽氧化工艺来生长厚的场氧化物，并且掺杂的离子是有源的并被驱动以同时形成掩埋的位线。 然后去除氮化硅层和焊盘氧化物层，并且通过使用场氧化物作为蚀刻掩模使硅衬底凹陷。 通过使用热氧化和蚀刻回流工艺对沟槽角进行四舍五入之后，重新生长薄的氮氧化硅膜。 沉积原位掺杂多晶硅膜以重新填充沟槽区域，然后通过使用CMP工艺来回蚀刻以形成浮动栅极。 接下来，顺序地构建诸如超薄ONO膜的互聚电介质，以及由n +掺杂多晶硅膜形成的控制栅极。 在定义字线之后，非易失性存储器被完成。

公开(公告)号：US5989977A

公开(公告)日：1999-11-23

申请号：US63210

申请日：1998-04-20

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/321 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/32105

Abstract: The present invention proposes a method for fabricating shallow trench regions for isolation. An oxide hard mask is utilized for the silicon etching. A thick thermal oxide film is created at and near the trench corners to prevent the gate wrap-around and corner parasitic leakage. Forming trench regions on a semiconductor substrate by using a thick pad oxide layer as an etching hard mask. A thermal oxide film is grown to recover the etching damages. An undoped LPCVD amorphous silicon film is then deposited on entire surface of the semiconductor substrate. A high temperature/pressure oxidation process follows to convert the undoped amorphous silicon film into thermal oxide. A thick CVD oxide layer is deposited on the semiconductor substrate. The oxide film outside the trench regions is removed by using a CMP process. Finally, the MOS devices are fabricated on the semiconductor substrate by standard processes, and thus complete the present invention.

Abstract translation: 本发明提出了一种用于制造用于隔离的浅沟槽区域的方法。 氧化物硬掩模用于硅蚀刻。 在沟槽角处和附近产生厚的热氧化膜，以防止栅极缠绕和拐角寄生泄漏。 通过使用厚焊盘氧化物层作为蚀刻硬掩模，在半导体衬底上形成沟槽区域。 生长热氧化膜以回收蚀刻损伤。 然后将未掺杂的LPCVD非晶硅膜沉积在半导体衬底的整个表面上。 接着进行高温/高压氧化处理，以将未掺杂的非晶硅膜转化为热氧化物。 在半导体衬底上沉积厚的CVD氧化物层。 通过使用CMP工艺除去沟槽区域外的氧化膜。 最后，通过标准工艺在半导体衬底上制造MOS器件，从而完成了本发明。

公开(公告)号：US5989950A

公开(公告)日：1999-11-23

申请号：US013676

申请日：1998-01-26

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: The present invention includes forming an oxide layer, nitride on a substrate. An ion implantation is performed. A LPD-oxide is formed on P well. Subsequently, an ion implantation to dope phosphorus into the substrate to form N well. Then, the LPD-oxide is removed. The oxide layer and the silicon nitride layer are respectively removed. Subsequently, a thin gate oxide is regrown on the surface of the substrate. A polysilicon layers, a second nitride are deposited on the oxide layer. Polysilicon gates are patterned. An ion implantation is carried out to implant arsenic into the P well. A thin LPD-oxide is forged along the surface of the gate, the substrate on the P well. A thermal anneal process is used to condense the LPD-oxide. Simultaneously, an ultra thin silicon oxynitride layer is formed on the surface of N well. Next, BSG side wall spacers are formed on the side walls of the gates. The silicon nitride layer is removed. Self-align silicide (SALICIDE), polycide are respectively formed on the exposed substrate, gates. Then, an ion implantation is performed. Then, another ion implantation is next used. Finally, ultra shallow junction source and drain are formed adjacent to the gates by using a rapid thermal process (RTP).

Abstract translation: 本发明包括在基板上形成氧化物层，氮化物。 进行离子注入。 在P阱上形成LPD氧化物。 随后，进行离子注入以将磷掺入底物以形成N。 然后，除去LPD-氧化物。 分别去除氧化物层和氮化硅层。 随后，在衬底的表面上重新生长薄栅氧化物。 多晶硅层，第二氮化物沉积在氧化物层上。 多晶硅栅极被图案化。 进行离子注入以将砷注入到P阱中。 沿着栅极的表面，P阱上的衬底锻造薄的LPD氧化物。 热退火工艺用于冷凝LPD氧化物。 同时，在N阱的表面上形成超薄氧氮化硅层。 接下来，在门的侧壁上形成BSG侧壁间隔物。 去除氮化硅层。 自对准硅化物（SALICIDE），多硅化物分别形成在暴露的基板上。 然后，进行离子注入。 然后，接下来使用另一种离子注入。 最后，通过使用快速热处理（RTP），在栅极附近形成超浅结点源极和漏极。

公开(公告)号：US5937281A

公开(公告)日：1999-08-10

申请号：US906552

申请日：1997-08-05

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L23/525 ,  H01L27/118 ,  H01L21/82

CPC classification number: H01L23/5252 ,  H01L27/11803 ,  H01L2924/0002

Abstract: A method of fabricating an antifuse structure for field programmable gate array (FPGA) applications is described. First, a field oxide layer for isolation is grown on the semiconductor silicon substrate. Then, a bottom electrode, a thin dielectric layer and a first top electrode layer are sequentially deposited on the surface of the field oxide layer. Next, a photoresist layer is coated on the surface of the first top electrode layer. Then, the first top electrode layer is patterned to form a top electrode stud. Next, a layer of silicon dioxide (SiO.sub.2) is deposited by Liquid Phase Deposition (LPD) to improve the overall profile of the antifuse structure. Thereafter, the photoresist pattern is removed. Next, a second top electrode layer is deposited overlaying the LPD-SiO.sub.2 layer and the top electrode stud. The top electrode that consists of the second top electrode layer and the top electrode stud is completed. The antifuse structure of FPGAs is accomplished.

Abstract translation: 描述了一种制造用于现场可编程门阵列（FPGA）应用的反熔丝结构的方法。 首先，在半导体硅衬底上生长用于隔离的场氧化物层。 然后，在场氧化物层的表面上依次沉积底电极，薄电介质层和第一顶电极层。 接下来，在第一顶电极层的表面上涂覆光致抗蚀剂层。 然后，将第一顶部电极层图案化以形成顶部电极柱。 接下来，通过液相沉积（LPD）沉积二氧化硅（SiO 2）层，以改善反熔丝结构的整体轮廓。 此后，去除光致抗蚀剂图案。 接下来，沉积覆盖LPD-SiO 2层和顶部电极柱的第二顶部电极层。 完成由第二顶电极层和顶电极柱组成的顶电极。 实现了FPGA的反熔丝结构。

公开(公告)号：US5933742A

公开(公告)日：1999-08-03

申请号：US708236

申请日：1996-09-06

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L28/91 ,  H01L27/10852 ,  H01L28/92

Abstract: A method of manufacturing multi-crown shape capacitors for use in semiconductor memories. The present invention uses the high etching selectivity between TEOS-oxide and polysilicon to fabricate the capacitor. using HSG-Si as an etching mask to etch the second dielectric layer to form dielectric pillars. An etching process is performed using the dielectric pillars as a mask to etching a portion of the first conductive layer and to etch away the remaining HSG-Si. Then side wall spacer are formed on the side walls of the dielectric pillars. Next, a selective etching process is used to define a multi-crown shape structure. Utilizing the pillars as a mold, the present invention can be used to form the multi-crown shaped structure to increase the surface area of the capacitor.

Abstract translation: 一种制造用于半导体存储器的多冠状电容器的方法。 本发明使用TEOS氧化物和多晶硅之间的高蚀刻选择性来制造电容器。 使用HSG-Si作为蚀刻掩模来蚀刻第二介电层以形成介电柱。 使用介电柱作为掩模进行蚀刻工艺，以蚀刻第一导电层的一部分并蚀刻剩余的HSG-Si。 然后在介电柱的侧壁上形成侧壁间隔物。 接下来，使用选择性蚀刻工艺来限定多冠形状结构。 利用支柱作为模具，本发明可用于形成多冠形结构以增加电容器的表面积。

公开(公告)号：US5929493A

公开(公告)日：1999-07-27

申请号：US52280

申请日：1998-03-31

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/0928 ,  H01L21/823892

Abstract: The present invention discloses a structure for forming CMOS transistors with a self-aligned planarization twin-well by using fewer mask counts. An N-well is formed in the semiconductor substrate. Then, a P-well is formed against the N-well, and portion of the P-well is formed along the bottom of the N-well. An oxide region is formed on the surface of both the N- and P-wells, and covers portions of the N- and P-wells. A high energy and low dose boron blanket implantation is performed to increase the threshold voltage of the oxide region, which has been used for an ESD (Electro-Static Discharge) protection circuit. Punch-through stopping layers for the CMOS transistor are formed in the upper portion of the N-well. A BF.sub.2 ion implantation layer is formed at the top of both the N- and P-wells to increase the threshold voltages of the PMOSFET and NMOSFET transistors. A pad oxide layer is also formed to cover the top of the N- and P-wells, and portions of the pad oxide layer are then formed to be the gate oxide layer of the PMOSFET and NMOSFET transistors.

Abstract translation: 本发明公开了一种通过使用更少的掩模计数来形成具有自对准平面化双阱的CMOS晶体管的结构。 在半导体衬底中形成N阱。 然后，相对于N阱形成P阱，并且沿着N阱的底部形成P阱的一部分。 在N阱和P阱的表面上形成氧化物区域，覆盖N阱和P阱的部分。 执行高能量和低剂量硼橡胶注入以增加已经用于ESD（静电放电）保护电路的氧化物区域的阈值电压。 用于CMOS晶体管的穿通停止层形成在N阱的上部。 在N阱和P阱的顶部形成BF 2离子注入层，以增加PMOSFET和NMOSFET晶体管的阈值电压。 还形成衬垫氧化物层以覆盖N阱和P阱的顶部，然后将衬垫氧化物层的部分形成为PMOSFET和NMOSFET晶体管的栅极氧化物层。