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公开(公告)号：US10321230B2
公开(公告)日：2019-06-11
申请号：US15482250
申请日：2017-04-07
Inventor： Tejasvi Das , Xin Zhao , Ku He , Xiaofan Fei
IPC: H04R3/00 , H03F99/00 , H03F1/02 , H03F3/21 , H03F3/217 , H03F3/30 , H03F3/72 , H03F3/185 , H04R29/00
Abstract: In accordance with embodiments of the present disclosure, a system may include a playback path and a control circuit. The playback path may have a playback input for receiving an input signal and configured to generate at a playback path output an output signal based on the input signal, wherein the playback path is configured to operate in a plurality of operational modes. The control circuit may be configured to receive a first signal from within the playback path and indicative of the input signal, receive a second signal generated from the input signal externally to the playback path, and select a selected operational mode from the plurality of operational modes based on the first signal and the second signal.
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公开(公告)号：US20190149096A1
公开(公告)日：2019-05-16
申请号：US16249619
申请日：2019-01-16
Inventor： Lei Zhu , Xin Zhao , John L. Melanson
Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
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公开(公告)号：US10263584B1
公开(公告)日：2019-04-16
申请号：US16133045
申请日：2018-09-17
Inventor： Tejasvi Das , Alan Mark Morton , Xin Zhao , Lei Zhu , Xiaofan Fei , Johann G. Gaboriau , John L. Melanson , Amar Vellanki
IPC: H03G3/30 , H03F3/187 , H04R3/00 , H03K17/687
Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
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公开(公告)号：US10224877B2
公开(公告)日：2019-03-05
申请号：US15581057
申请日：2017-04-28
Inventor： Lei Zhu , Xin Zhao , John L. Melanson
IPC: H03F3/38 , H03F1/02 , H03F1/56 , H03F3/183 , H03F3/217 , H03G3/30 , H03F1/30 , H03F1/32 , H03F3/187 , H03M1/66
Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
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公开(公告)号：US10008992B1
公开(公告)日：2018-06-26
申请号：US15487555
申请日：2017-04-14
Inventor： Lei Zhu , Xin Zhao , Alan Mark Morton , Tejasvi Das , Ku He , Xiaofan Fei
CPC classification number: H03F3/2178 , H03F1/0277 , H03F3/30 , H03F2200/03 , H03F2200/411 , H03F2200/432
Abstract: An amplifier may include a final output stage switchable among a plurality of modes comprising a mode which is enabled by coupling an output driver to an output of the final output stage and a preconditioning circuit coupled to the output of the final output stage. The preconditioning circuit may be configured to precondition at least one of a voltage and a current of the output of the final output stage prior to coupling the output driver to the output of the final output stage to limit audio artifacts caused by switching the final output stage to the mode or may be configured to perform a switching sequence to switch between a first mode and a second mode of the plurality of modes, such that at all points of the switching sequence, output terminals of the output of the final output stage have a known impedance.
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Patent Agency Ranking
公开(公告)号：US10727860B1
公开(公告)日：2020-07-28
申请号：US16522033
申请日：2019-07-25
Inventor： Wai-Shun Shum , Lei Zhu , Johann G. Gaboriau , Xiaofan Fei , Xin Zhao
IPC: H03M3/00
Abstract: A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.
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公开(公告)号：US10404248B2
公开(公告)日：2019-09-03
申请号：US16219187
申请日：2018-12-13
Inventor： Tejasvi Das , Alan Mark Morton , Xin Zhao , Lei Zhu , Xiaofan Fei , Johann G. Gaboriau , John L. Melanson , Amar Vellanki
Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
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公开(公告)号：US10320337B2
公开(公告)日：2019-06-11
申请号：US15418405
申请日：2017-01-27
Inventor： Xin Zhao , Tejasvi Das , Hossein Mirzaie , Lei Zhu , Xiaofan Fei
Abstract: A dynamic common reference input (CMRI) signal may be provided to an operational amplifier, or “op-amp,” in an amplifier system to reduce the common mode ripple of the fully-differential op-amp, while adding little or no noise in the amplifier system. The dynamic CMRI signal may be controlled such that a common-mode component of two amplifier input nodes of the operational amplifier is made approximately independent of two input signals received at two system input nodes of the amplifier system. An amplifier system with the dynamic CMRI may be used in class-D amplifiers, such as amplifiers for audio systems that generate output for headphones or speakers.
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公开(公告)号：US09929703B1
公开(公告)日：2018-03-27
申请号：US15277465
申请日：2016-09-27
Inventor： Xin Zhao , Tejasvi Das , Xiaofan Fei , Alan Mark Morton
CPC classification number: H03F3/2171 , H03F1/32 , H03F1/342 , H03F3/181 , H03F3/187 , H03F3/217 , H03F3/2173 , H03F3/38 , H03F3/72 , H03F2200/345 , H03F2200/351
Abstract: An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.
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公开(公告)号：US09917557B1
公开(公告)日：2018-03-13
申请号：US15488979
申请日：2017-04-17
Inventor： Lei Zhu , Xin Zhao , Tejasvi Das , Alan Mark Morton , Xiaofan Fei
CPC classification number: H03F3/2178 , H03F1/0277 , H03F3/187 , H03F3/211 , H03F3/2171 , H03F3/72 , H03F2200/03 , H03F2200/321 , H03F2200/375 , H03F2200/411
Abstract: A method for offset calibration may include decoupling a modulator input of a first path from a first stage output, coupling a second path output to the modulator input, applying a common-mode voltage to a second path input, receiving a calibration signal from the modulator output generated in response to the common-mode voltage, and modifying one or more parameters of the modulator to compensate for an offset between the first path and the second path indicated by the calibration signal. A method for gain calibration may include decoupling a modulator input from a first stage output, decoupling a second path from the first stage output, applying a first test signal to the modulator input, applying a second test signal to a second path input, wherein the second test signal is of opposite phase as the first test signal, coupling a second path output to an amplifier input via a calibration feedback network, receiving a calibration signal from the first stage output generated in response to the first test signal and the second test signal, and modifying one or more parameters of the second path to compensate for a difference in respective gains of the modulator and the second path indicated by the calibration signal.
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