公开(公告)号：US11029475B2

公开(公告)日：2021-06-08

申请号：US16522531

申请日：2019-07-25

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. Patel ,  Aparna R. Prasad ,  Sandeep Razdan

IPC: G02B6/42

Abstract: The present disclosure provides a frame lid assembly, which may be used in assembling an optical platform to provide isolated thermal conduction paths for various elements thereof. The frame lid assembly includes a first frame lid, including: a foot, disposed in a first plane; a roof, disposed in a second plane parallel to the first plane, the roof defining a port as a first through-hole that is perpendicular to the second plane; a wall, disposed obliquely to the first plane, separating the roof from the foot, the wall defining a slot as a second through-hole that is parallel to the first plane; a second frame lid connected to the first frame lid and thermally isolated from the first frame lid, the second frame lid including: a cap, connected to the roof via a thermal insulator; and a plug, extending perpendicularly from the cap through the port.

公开(公告)号：US11906824B2

公开(公告)日：2024-02-20

申请号：US18177497

申请日：2023-03-02

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan Zhang ,  Vipulkumar K. Patel ,  Prakash B. Gothoskar ,  Ming Gai Stanley Lo

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2202/104 ,  G02F2202/105

Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.

公开(公告)号：US11810877B2

公开(公告)日：2023-11-07

申请号：US17454937

申请日：2021-11-15

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. Patel ,  Mark A. Webster ,  Craig S. Appel

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/522 ,  H01L21/20 ,  G02B6/122 ,  G02B6/12 ,  G02B6/30

CPC classification number: H01L24/01 ,  H01L21/2007 ,  H01L23/5222 ,  G02B6/1225 ,  G02B6/305 ,  G02B2006/12061

Abstract: Embodiments herein describe providing a decoupling capacitor on a first wafer (or substrate) that is then bonded to a second wafer to form an integrated decoupling capacitor. Using wafer bonding means that the decoupling capacitor can be added to the second wafer without having to take up space in the second wafer. In one embodiment, after bonding the first and second wafers, one or more vias are formed through the second wafer to establish an electrical connection between the decoupling capacitor and bond pads on a first surface of the second wafer. An electrical IC can then be flip chipped bonded to the first surface. As part of coupling the decoupling capacitor to the electrical IC, the decoupling capacitor is connected between the rails of a power source (e.g., VDD and VSS) that provides power to the electrical IC.

公开(公告)号：US11728622B2

公开(公告)日：2023-08-15

申请号：US16290698

申请日：2019-03-01

Applicant: Cisco Technology, Inc.

Inventor： Dominic F. Siriani ,  Vipulkumar K. Patel ,  Matthew J. Traverso ,  Mark A. Webster

IPC: H01S5/10 ,  H01S5/34 ,  H01S5/50 ,  H01S5/22 ,  H01S5/14

CPC classification number: H01S5/101 ,  H01S5/1003 ,  H01S5/1014 ,  H01S5/22 ,  H01S5/34 ,  H01S5/341 ,  H01S5/50 ,  H01S5/1025 ,  H01S5/146

Abstract: An optical apparatus comprises a semiconductor substrate and an optical waveguide emitter. The optical waveguide emitter comprises an input waveguide section extending from a facet of the semiconductor substrate, a turning waveguide section optically coupled with the input waveguide section, and an output waveguide section extending to the same facet and optically coupled with the turning waveguide section. One or more of the input waveguide section, the turning waveguide section, and the output waveguide section comprises an optically active region.

公开(公告)号：US11728616B2

公开(公告)日：2023-08-15

申请号：US17444202

申请日：2021-08-02

Applicant: Cisco Technology, Inc.

Inventor： Jock T. Bovington ,  Vipulkumar K. Patel ,  Dominic F. Siriani

IPC: H01S5/02 ,  H01S5/042 ,  H01S5/343 ,  H01S5/40 ,  H01S5/34 ,  G02B6/42

CPC classification number: H01S5/0215 ,  H01S5/021 ,  H01S5/0218 ,  H01S5/042 ,  H01S5/343 ,  H01S5/3412 ,  H01S5/4025 ,  G02B6/42 ,  G02B6/4234

Abstract: A laser integrated photonic platform to allow for independent fabrication and development of laser systems in silicon photonics. The photonic platform includes a silicon substrate with an upper surface, one or more through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate. The photonic platform includes a silicon substrate wafer with through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate for mating the photonic platform to a photonics integrated circuit. The photonic platform also includes a III-V semiconductor material structure wafer, where the III-V wafer is bonded to the upper surface of the silicon substrate and includes at least one active layer forming a light source for the photonic platform.

公开(公告)号：US11555972B2

公开(公告)日：2023-01-17

申请号：US17303853

申请日：2021-06-09

Applicant: Cisco Technology, Inc.

Inventor： Norbert Schlepple ,  Vipulkumar K. Patel ,  Anthony D. Kopinetz

IPC: G02B6/42

Abstract: Aspects described herein include an apparatus supporting optical alignment with one or more optical waveguides optically exposed along an edge of a photonic integrated circuit (IC). The apparatus comprises a frame body comprising an upper portion defining a reference surface, and a lateral portion defining an interface for an optical connector connected with one or more optical fibers. The lateral portion comprises one or more optical components defining an optical path through the lateral portion. The one or more optical components are arranged relative to the reference surface such that the one or more optical components align with (i) the one or more optical waveguides along at least one dimension when the reference surface contacts a top surface of an anchor IC, and with (ii) the one or more optical fibers when the optical connector is connected at the interface.

公开(公告)号：US11480730B2

公开(公告)日：2022-10-25

申请号：US17304227

申请日：2021-06-16

Applicant: Cisco Technology, Inc.

Inventor： Alexey V. Vert ,  Vipulkumar K. Patel ,  Mark A. Webster

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/136 ,  G02B6/293 ,  G02B6/30

Abstract: A method includes defining a first waveguide in a first region of an optical device over a first dielectric layer over a silicon on insulator (SOI) substrate of the optical device and disposing a second dielectric layer on the first waveguide and the first dielectric layer of the optical device. The method also includes defining a second region on the second dielectric layer, the first dielectric layer, and the SOI substrate. The second region includes an integrated trench structure defined in the SOI substrate. The method further includes etching the second region to form an etched second region, disposing a third dielectric layer in the etched second region, and disposing a second waveguide on at least the third dielectric layer. The second waveguide is disposed to provide an optical coupling between the second waveguide and the first waveguide.

公开(公告)号：US11418005B2

公开(公告)日：2022-08-16

申请号：US16581923

申请日：2019-09-25

Applicant: Cisco Technology, Inc.

Inventor： Dominic F. Siriani ,  Vipulkumar K. Patel ,  Jock T. Bovington ,  Matthew J. Traverso

IPC: H01S5/00 ,  H01S5/026 ,  H01S3/23 ,  H01L31/0304 ,  G02B6/12 ,  H01S5/14 ,  H01S5/10 ,  H01S5/50 ,  H01S5/028 ,  H01S5/02

Abstract: Described herein is a two chip photonic device (e.g., a hybrid master oscillator power amplifier (MOPA)) where a gain region and optical amplifier region are formed on a III-V chip and a variable reflector (which in combination with the gain region forms a laser cavity) is formed on a different semiconductor chip that includes silicon, silicon nitride, lithium niobate, or the like. Sides of the two chips are disposed in a facing relationship so that optical signals can transfer between the gain region, the variable reflector, and the optical amplifier.

公开(公告)号：US11018473B1

公开(公告)日：2021-05-25

申请号：US16203463

申请日：2018-11-28

Applicant: Cisco Technology, Inc.

Inventor： Dominic F. Siriani ,  Jock T. Bovington ,  Vipulkumar K. Patel

IPC: H01S5/026 ,  H01S5/343 ,  H01S5/02 ,  G02B6/136 ,  G02B6/122 ,  H01S5/028 ,  H01S5/10 ,  G02B6/13 ,  G02B6/12

Abstract: Embodiments provide for selective-area growth of III-V materials for integration with silicon photonics. The resulting platform includes a substrate; an insulator, extending a first distance from the substrate, including a passive optical component at a second distance from the substrate less than the first distance, and defining a pit extending to the substrate; and a III-V component, extending from the substrate within in the pit defined in the insulator, the III-V component including a gain medium included at the second distance from the substrate and optically coupled with the passive optical component. The pit may define an Optical Coupling Interface between the III-V component and the passive optical component, or a slit defined between the III-V component and the passive optical component may define the Optical Coupling Interface.