公开(公告)号：US06413881B1

公开(公告)日：2002-07-02

申请号：US09521312

申请日：2000-03-09

Applicant: Sheldon Aronowitz ,  John Haywood ,  James P. Kimball ,  Helmut Puchner ,  Ravindra Manohar Kapre ,  Nicholas Eib

Inventor： Sheldon Aronowitz ,  John Haywood ,  James P. Kimball ,  Helmut Puchner ,  Ravindra Manohar Kapre ,  Nicholas Eib

IPC: H01L2131

CPC classification number: H01L21/28176 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/3144 ,  H01L29/518

Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.

Abstract translation: 抑制掺杂剂从栅电极通入薄栅氧化物的方法包括在栅极氧化物上形成栅电极之前，对薄栅极氧化物的上表面进行氮化，从而形成氮原子的势垒 栅极氧化物的上表面区域与栅极氧化物和栅电极之间的界面相邻，以在结构退火期间抑制掺杂剂原子从栅电极到薄栅氧化层的通过。 在一个实施例中，可以蚀刻硅衬底上的氧化硅的选择性部分，以使用施加到硅衬底的偏压的氮等离子体将氧化物稀释至期望的厚度。 然后通过从硅衬底去除偏压，在相同的装置中进行蚀刻的氧化硅的表面的氮化。

公开(公告)号：US06246093B1

公开(公告)日：2001-06-12

申请号：US08719773

申请日：1996-09-25

Applicant: Lindor E. Henrickson ,  Sheldon Aronowitz

Inventor： Lindor E. Henrickson ,  Sheldon Aronowitz

IPC: H01L2978

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/7835 ,  H01L29/7838

Abstract: A MOSFET having a buried channel structure and an adjacent surface channel structure between a source region and a drain region. The surface channel structure is preferably formed adjacent the source region via angular implantation techniques. By combining the advantages of the surface channel device with the buried channel device, the resulting hybrid MOSFET structure has improved drive current and switching characteristics.

Abstract translation: 具有掩埋沟道结构的MOSFET和源极区域和漏极区域之间的相邻表面沟道结构。 表面通道结构优选通过角度注入技术形成在源区附近。 通过结合表面沟道器件与掩埋沟道器件的优点，所得到的混合MOSFET结构具有改进的驱动电流和开关特性。

公开(公告)号：US6156620A

公开(公告)日：2000-12-05

申请号：US121283

申请日：1998-07-22

Applicant: Helmut Puchner ,  Shih-Fen Huang ,  Sheldon Aronowitz

Inventor： Helmut Puchner ,  Shih-Fen Huang ,  Sheldon Aronowitz

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76232

Abstract: An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.

Abstract translation: 在硅半导体衬底中的隔离沟槽设置有阻挡区域，该阻挡区域包含在沟槽中形成的与沟槽的硅半导体衬底表面相邻的氮原子。 本发明的新型隔离沟槽结构通过在硅半导体衬底中形成隔离沟槽而形成; 通过用氮等离子体的氮原子处理沟槽结构，在隔离沟槽中形成阻挡区; 然后在沟槽中的阻挡区域上形成氧化硅层以将氮原子限制在阻挡区域中。 在优选实施例中，首先在沟槽的硅半导体衬底表面上形成氧化硅衬垫，然后用氮等离子体的氮原子处理沟槽结构，以在沟槽的硅半导体衬底表面上形成 含有硅原子，氧原子和氮原子的阻挡层。

公开(公告)号：US6093936A

公开(公告)日：2000-07-25

申请号：US918577

申请日：1997-08-19

Applicant: Abraham Yee ,  Sheldon Aronowitz ,  Yu-Lam Ho

Inventor： Abraham Yee ,  Sheldon Aronowitz ,  Yu-Lam Ho

IPC: H01L21/265 ,  H01L21/762 ,  H01L27/06 ,  H01L29/04

CPC classification number: H01L27/0688 ,  H01L21/26506 ,  H01L21/76213

Abstract: A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles. Also, the amorphous silicon relieves surface layer stresses which may be present from prior processes or because of prior morphological structural elements formed on the silicon substrate. A boron ion bombardment may also be used to further inhibit loss of P-well dopant to the oxidant forming the field oxidation layer and preserving a desired high field threshold voltage and robust field isolation for the integrated circuit.

Abstract translation: 硅半导体集成电路包括基本上不会侵入集成电路的有源电路元件的绝缘场氧化层。 场氧化层由通过用惰性气体离子轰击硅衬底产生的氧化非晶硅形成。 非晶硅以比结晶硅更快的速度氧化，使得当形成场氧化层时，用于有源电路元件的晶体硅基底基本保持不变。 在惰性气体离子轰击期间，通过使用适当的屏蔽元件形成晶体硅基底。 这种惰性气体离子轰击还具有消除场氧化区域中可能存在的位错缺陷的优点，使得这些缺陷在随后的加热和冷却循环期间不会传播到硅的晶格中。 此外，非晶硅减轻了可能存在于现有工艺中的表面层应力或由于在硅衬底上形成的先前形态结构元件。 还可以使用硼离子轰击来进一步抑制形成场氧化层的氧化剂的P阱掺杂剂的损失，并且为集成电路保留期望的高场阈值电压和鲁棒的场隔离。

公开(公告)号：US6033998A

公开(公告)日：2000-03-07

申请号：US38684

申请日：1998-03-09

Applicant: Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

Inventor： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

IPC: H01L21/8234 ,  H01L21/76

CPC classification number: H01L21/823462

Abstract: Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.

Abstract translation: 提供一种制造在半导体晶片的不同区域上具有可变厚度和组成的栅极电介质层的方法。 在本发明的优选实施例中，首先在各个区域上生长栅氧化层。 具有相对较厚，未硬化的栅极电介质的区域被掩蔽，并且晶片暴露于远程低能量氮等离子体。 在氮化处理完成之后，去除掩模并使晶片进一步氧化。 已经形成氮氧化物的区域用作氧化过程的屏障。 因此，可以在相同的晶片上生长不同的氧化物厚度，在已经进行氮化的情况下更薄并且硬化，并且在氮化期间被掩蔽的那些区域中较厚而不硬化。 根据本发明的可变厚栅极电介质在涉及数字和模拟装置的半导体集成电路中可能是特别有利的。

公开(公告)号：US5904551A

公开(公告)日：1999-05-18

申请号：US631360

申请日：1996-04-12

Applicant: Sheldon Aronowitz ,  James Kimball

Inventor： Sheldon Aronowitz ,  James Kimball

IPC: H01L21/265 ,  H01L21/70

CPC classification number: H01L21/26513 ,  H01L21/26586

Abstract: A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Abstract translation: 公开了一种用于通过以低能量注入（包括使半导体衬底的晶格定向）来在单晶半导体衬底的表面下方形成一个或多个掺杂区域（例如逆行阱或较深源极/漏极区域）的方法， 到注入光束的轴线，即注入光束中的激发原子的路径，以使在晶格中的原子之间通过的注入原子的数量最大化。 这导致单晶半导体衬底的晶格中的注入原子的峰值浓度比衬底中注入原子的峰值浓度更深，如果注入光束的轴不相对于晶格取向 的半导体衬底。

公开(公告)号：US5707888A

公开(公告)日：1998-01-13

申请号：US434674

申请日：1995-05-04

Applicant: Sheldon Aronowitz ,  James Kimball

Inventor： Sheldon Aronowitz ,  James Kimball

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S438/911

Abstract: A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer. The initial oxide formed by the process appears to be temperature independent, at temperatures of 900.degree. C. or less, with oxide formation apparently dependent upon the extent of the implanted regions of the substrate, rather than upon temperature, resulting in thermal savings. Furthermore, the excess implanted noble gas in the substrate adjacent the oxide formed therein can have beneficial effects in inhibiting the formation of parasitic field transistors and in greater control over field thresholds.

公开(公告)号：US5357135A

公开(公告)日：1994-10-18

申请号：US198686

申请日：1994-02-18

Applicant: Sheldon Aronowitz ,  George P. Walker ,  Peter Meng ,  Farrokh Mohammadi ,  Bhaskar V. S. Gadepally

Inventor： Sheldon Aronowitz ,  George P. Walker ,  Peter Meng ,  Farrokh Mohammadi ,  Bhaskar V. S. Gadepally

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L29/7802 ,  H01L29/0847

Abstract: Body to drain junction breakdown, due to avalanching in DMOST devices, can be controlled. The invention lowers the electric field gradients in the vicinity of the PN junction. The structure employed to enhance breakdown behavior is specifically applied to a vertical DMOST. The N type doping profile in the vicinity of the body to drain junction is tailored by constructing a P-nu-N-N.sup.+ type diode structure where nu is a low N type impurity concentration region. The N type region is of higher impurity concentration and is more extensive. With the nu region having one-half of the impurity concentration of the N region and an extent of about two microns, the avalanche breakdown voltage is about 27% higher than the conventional PN junction diode. By making the nu region impurity concentration one-fourth that of the N region, the breakdown voltage is 40% higher.

Abstract translation: 由于DMOST装置中的雪崩，可以控制体漏排结。 本发明降低PN结附近的电场梯度。 用于增强击穿行为的结构特别适用于垂直DMOST。 通过构造其中nu为低N型杂质浓度区域的P-nu-N-N +型二极管结构，来调整体侧与漏极结附近的N型掺杂分布。 N型区域的杂质浓度较高，更为广泛。 在nu区域具有N区域的杂质浓度的一半和约2微米的范围内，雪崩击穿电压比常规PN结二极管高约27％。 通过使nu区杂质浓度为N区的四分之一，击穿电压高40％。

公开(公告)号：US5296387A

公开(公告)日：1994-03-22

申请号：US984889

申请日：1992-12-02

Applicant: Sheldon Aronowitz ,  Courtney Hart

Inventor： Sheldon Aronowitz ,  Courtney Hart

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/316 ,  H01L21/336 ,  H01L29/161

CPC classification number: H01L21/26506 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/28525 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/66568 ,  Y10S148/058 ,  Y10S148/059

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming a germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Abstract translation: 锗用于显着增强带硅衬底的N沟道和P沟道金属氧化物半导体（MOS）晶体管通道中少数载流子的漂移迁移率。 锗处理也用于增强MOS器件的源/漏接触电导。 公开了利用锗注入和湿氧化形成富含锗的界面层的方法，或通过分子束外延生长硅 - 锗合金。

公开(公告)号：US5192712A

公开(公告)日：1993-03-09

申请号：US868808

申请日：1992-04-15

Applicant: Sheldon Aronowitz ,  Amolak Ramde

Inventor： Sheldon Aronowitz ,  Amolak Ramde

IPC: C23C14/48 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/761

CPC classification number: H01L21/761 ,  H01L21/22 ,  H01L21/2253

Abstract: A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.