-
21.发明授权公开(公告)号：US10068180B2
公开(公告)日：2018-09-04
申请号：US14896259
申请日：2013-10-22
Applicant: D-Wave Systems Inc.
Inventor： Mohammad H. S. Amin , Andrew J. Berkley , Richard G. Harris , Trevor Michael Lanting , Anatoly Yu Smirnov
Abstract: Systems and methods for employing macroscopic resonant tunneling operations in quantum processors are described. New modes of use for quantum processor architectures employ probe qubits to determine energy eigenvalues of a problem Hamiltonian through macroscopic resonant tunneling operations. A dedicated probe qubit design that may be added to quantum processor architectures is also described. The dedicated probe qubit enables improved performance of macroscopic resonant tunneling operations and, consequently, improved performance of the new modes of use described.
-
公开(公告)号：US12099901B2
公开(公告)日：2024-09-24
申请号：US18243280
申请日：2023-09-07
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris
CPC classification number: G06N10/00 , G06F15/7867 , G06N10/40
Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
-
公开(公告)号：US20240070497A1
公开(公告)日：2024-02-29
申请号：US18243280
申请日：2023-09-07
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris
CPC classification number: G06N10/00 , G06F15/7867 , G06N10/40
Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
-
24.发明公开公开(公告)号：US20230370069A1
公开(公告)日：2023-11-16
申请号：US17883874
申请日：2022-08-09
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mohammad H. Amin , Richard G. Harris
IPC: H03K19/195 , G06N10/40
CPC classification number: H03K19/195 , G06N10/40
Abstract: A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.
-
25.发明授权公开(公告)号：US11730066B2
公开(公告)日：2023-08-15
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
-
Patent Agency Ranking
公开(公告)号：US20230027682A1
公开(公告)日：2023-01-26
申请号：US17786192
申请日：2020-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Emile M. Hoskinson , Richard G. Harris , Trevor M. Lanting , Paul I. Bunyk , Andrew J. Berkley
Abstract: An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
-
公开(公告)号：US11031537B2
公开(公告)日：2021-06-08
申请号：US16380751
申请日：2019-04-10
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
-
公开(公告)号：US11023821B2
公开(公告)日：2021-06-01
申请号：US15881260
申请日：2018-01-26
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Kelly T. R. Boothby , Andrew D. King
Abstract: A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.
-
公开(公告)号：US20190228331A1
公开(公告)日：2019-07-25
申请号：US16258082
申请日：2019-01-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Paul I. Bunyk , Mohammad H.S. Amin , Emile M. Hoskinson
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
-
公开(公告)号：US20180314970A1
公开(公告)日：2018-11-01
申请号：US16029040
申请日：2018-07-06
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Mohammad H. Amin , Anatoly Smirnov
IPC: G06N99/00 , H03K19/195
CPC classification number: G06N99/002 , G11C11/44 , H03K3/38 , H03K19/1952
Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.
-
-
-
-
-
-
-
-
-
Search Results
56
records
(took 0.029 seconds)
