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公开(公告)号：US09182433B2
公开(公告)日：2015-11-10
申请号：US13936250
申请日：2013-07-08
Applicant: DENSO CORPORATION
Inventor： Tomohiro Nezuka
CPC classification number: G01R27/2605 , G01N27/228
Abstract: A detection circuit for a capacitive sensor includes a drive signal generator for applying drive signal varying between first and second levels to a sensor common terminal, a sense amplifier having input terminals respectively connected to sensor detection terminals, and a controller for controlling input common-mode voltage of the sense amplifier to predetermined voltage. The controller includes a feedback amplifier for outputting feedback voltage according to difference between the common-mode and predetermined voltages, a pair of feedback capacitors having one ends respectively connected to the detection terminals and another ends connected together, and a voltage switcher for applying preset voltage, between the predetermined voltage and a limit voltage outputtable by the feedback amplifier in direction where the second level exists relative to the first level, to the other ends during the first level and the feedback voltage to the other ends during the second level.
Abstract translation: 一种用于电容式传感器的检测电路，包括驱动信号发生器，用于将驱动信号在第一和第二电平之间变化到传感器公共端，具有分别连接到传感器检测端的输入端的读出放大器和用于控制输入共模的控制器 读出放大器的电压到预定电压。 控制器包括反馈放大器，用于根据共模和预定电压之间的差异输出反馈电压;一对反馈电容器，其一端分别连接到检测端子，另一端连接在一起;以及电压切换器，用于施加预设电压 在所述预定电压和所述反馈放大器在所述第二电平相对于所述第一电平存在的方向上输出的限制电压之间，在所述第一电平期间的另一端和在所述第二电平期间的另一端的反馈电压之间。
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公开(公告)号：US09110114B2
公开(公告)日：2015-08-18
申请号：US13936256
申请日：2013-07-08
Applicant: DENSO CORPORATION
Inventor： Tomohiro Nezuka
CPC classification number: G01R27/2605 , G01D5/2417
Abstract: A detection circuit for a capacitive sensor includes a drive signal generator for applying drive signal to a sensor common terminal, a sense amplifier having input terminals respectively connected to sensor detection terminals, and a controller for controlling input common-mode voltage of the sense amplifier to predetermined voltage. The controller includes a feedback amplifier for outputting feedback voltage according to difference between the common-mode and predetermined voltages, a pair of first feedback capacitors having one ends respectively connected to the detection terminals and another ends connected together, a second feedback capacitor having one end connected to the other ends, and a voltage switcher for applying first preset voltage to the other ends during first level of the drive signal and for applying second preset voltage to the other ends and the predetermined voltage to another end of the second feedback capacitor during second level of the drive signal.
Abstract translation: 用于电容式传感器的检测电路包括用于向传感器公共端施加驱动信号的驱动信号发生器，具有分别连接到传感器检测端的输入端的读出放大器和用于控制读出放大器的输入共模电压的控制器 预定电压。 控制器包括反馈放大器，用于根据共模和预定电压之间的差异输出反馈电压;一对第一反馈电容器，其一端分别连接到检测端子，另一端连接在一起;第二反馈电容器，其一端 连接到另一端，以及电压切换器，用于在驱动信号的第一级中将第一预设电压施加到另一端，并且在第二级期间将另一端施加第二预设电压并将预定电压施加到第二反馈电容器的另一端 驱动信号的电平。
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公开(公告)号：US12063053B2
公开(公告)日：2024-08-13
申请号：US17877241
申请日：2022-07-29
Applicant: DENSO CORPORATION
Inventor： Yuu Fujimoto , Tomohiro Nezuka , Kunihiko Nakamura
Abstract: An analog-to-digital converter includes a primary converter and a secondary converter. The primary converter executes conversion processing to convert an analog input signal to a first digital signal through delta-sigma modulation. The secondary converter outputs a second digital signal by converting amplified analog output of a quantization error in the primary converter to the second digital signal.
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公开(公告)号：US11848677B2
公开(公告)日：2023-12-19
申请号：US17884871
申请日：2022-08-10
Inventor： Shotaro Wada , Tomohiro Nezuka
CPC classification number: H03K5/003 , H03K5/15013 , H03K5/15026 , H03K21/00 , H03K2005/00013
Abstract: A clock signal generation circuit for a switched capacitor circuit with a chopping function unit includes: first and second synchronous clock circuits that generate first and second synchronous clock signals, respectively; an edge signal generation circuit that generates one or more rise and fall edge signals by delaying the first synchronous clock signal; a first clock generator that generate a first clock signal group for driving the switched capacitor circuit; and a second clock generator that generates a second clock signal group for driving the chopping function unit. Frequencies of the first and second clock signal groups are respectively defined by the first and second synchronous clock circuits. Rise and fall edges of the first and second clock signal groups are defined by the edge signal generation circuit.
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公开(公告)号：US11831302B2
公开(公告)日：2023-11-28
申请号：US17550887
申请日：2021-12-14
Applicant: DENSO CORPORATION
Inventor： Yuuta Nakamura , Yasuaki Aoki , Hideji Yoshida , Takashi Yoshiya , Tomohiro Nezuka , Akimasa Niwa
IPC: H03K17/042 , H02M1/08 , H02M1/00 , H02M7/537 , H03K17/687
CPC classification number: H03K17/04206 , H02M1/0009 , H02M1/08 , H02M7/537 , H03K17/687
Abstract: A drive circuit drives a switch configuring a power converter. The drive circuit divides an inter-terminal voltage of a switch. The drive circuit includes a differential circuit having first and second input terminals to which the divided inter-terminal voltages are inputted. The differential circuit outputs an analog voltage based on a voltage difference between the input terminals. The differential circuit executes reset of the output voltage, and with the voltage difference when reset is canceled after reset is executed as a reference voltage, outputs an analog voltage in which an amount of change from the reference voltage is multiplied by an amplification factor. The drive circuit outputs a binary signal based on comparison results between a threshold and the analog voltage outputted from the differential circuit, and sets a transfer rate of a gate charge of the switch when a driving state is switched, based on the output signal thereof.
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Patent Agency Ranking
公开(公告)号：US10804920B2
公开(公告)日：2020-10-13
申请号：US16596927
申请日：2019-10-09
Applicant: DENSO CORPORATION
Inventor： Kunihiko Nakamura , Yu Fujimoto , Tomohiro Nezuka
Abstract: An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits. A sum of the most significant bits and the least significant bits are output as an output signal. Initialization of the charge of the integration capacitor, the charge transfer operation for a next A/D conversion, and generation of the most significant bits are performed in parallel with the A/D conversion in the sub-A/D converter after the generation of the most significant bits.
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公开(公告)号：US10790851B2
公开(公告)日：2020-09-29
申请号：US16533849
申请日：2019-08-07
Applicant: DENSO CORPORATION
Inventor： Tomohiro Nezuka
IPC: H03M3/00
Abstract: A ΔΣ modulator includes: an integrator having an operational amplifier and an integral capacitor; a quantizer outputting a quantization result; a D/A converter connected to a first input terminal of the operational amplifier through a first control switch, and subtracting an electric charge based on the quantization result from an electric charge stored in the integral capacitor to perform feedback of the quantization result to the integrator; a control circuit outputting a digital output value; and a sampling capacitor being connected to the first input terminal through a second control switch. The second control switch switches on and off an electrical connection between the sampling capacitor and the intermediate point between the integral capacitor and first input terminal, and plural feedbacks of the quantization results are performed per one sampling cycle.
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公开(公告)号：US10735016B2
公开(公告)日：2020-08-04
申请号：US16555042
申请日：2019-08-29
Applicant: DENSO CORPORATION
Inventor： Kunihiko Nakamura , Tomohiro Nezuka
Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.
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公开(公告)号：US10484003B2
公开(公告)日：2019-11-19
申请号：US16224213
申请日：2018-12-18
Applicant: DENSO CORPORATION
Inventor： Tomohiro Nezuka
Abstract: An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.
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公开(公告)号：US09077373B1
公开(公告)日：2015-07-07
申请号：US14595400
申请日：2015-01-13
Applicant: DENSO CORPORATION
Inventor： Tomohiro Nezuka
IPC: H03M3/00
Abstract: An A/D conversion apparatus includes a signal processor, a quantizer, and a controller. The signal processor has circuit blocks connected in a loop to process an analog input signal. The quantizer generates a quantization value by quantizing an output of at least one of the circuit blocks including a final-stage circuit block. In each circuit block, one end of a first capacitor is connected through a switch to an input terminal of an operational amplifier, and one end of each of second and third capacitors is connected directly to the operational amplifier. The controller generates an A/D conversion result of the analog input signal according to the quantization value and changes connection conditions of the capacitors so that the signal processor and the quantizer function as a delta-sigma modulator or a cyclic A/D converter.
Abstract translation: A / D转换装置包括信号处理器，量化器和控制器。 信号处理器具有以循环连接的电路块来处理模拟输入信号。 量化器通过量化包括最后级电路块的至少一个电路块的输出来产生量化值。 在每个电路块中，第一电容器的一端通过开关连接到运算放大器的输入端，第二和第三电容器的一端直接连接到运算放大器。 控制器根据量化值产生模拟输入信号的A / D转换结果，并改变电容器的连接条件，使得信号处理器和量化器用作Δ-Σ调制器或循环A / D转换器。
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