公开(公告)号：US20090290414A1

公开(公告)日：2009-11-26

申请号：US12512829

申请日：2009-07-30

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5642

摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.

摘要翻译： 非易失性半导体存储器件包括具有串联连接的多个多电平存储单元的存储单元阵列。 多个多级存储器单元形成多个阈值分布，每个阈值分布对应于较低位的状态和高位的状态，其中低位和高位分别构成下部页面和上部页面 。 较低位的状态将阈值分布分为两组，高位的状态进一步将两组中的每一组进行二分。 当对上部页面的存储单元进行编程时，当对下部页面的存储单元进行编程时，较高电位被施加到与所选字线相邻的未选择字线，而不是应用于未选择的字线。

公开(公告)号：US07586785B2

公开(公告)日：2009-09-08

申请号：US12020981

申请日：2008-01-28

申请人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

发明人： Koji Hosono ,  Kenichi Imamiya ,  Hiroshi Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/105 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C2216/14

摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

摘要翻译： 一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路 的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和 从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在 读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。

公开(公告)号：US07567463B2

公开(公告)日：2009-07-28

申请号：US12123157

申请日：2008-05-19

申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

公开(公告)号：US20090080264A1

公开(公告)日：2009-03-26

申请号：US12252896

申请日：2008-10-16

申请人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

发明人： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC分类号： G11C16/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G06F3/0659 ,  G06F12/0246 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/104 ,  G11C2216/14

摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

摘要翻译： 在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否 或者不是第二操作是可执行的。

公开(公告)号：US20090061607A1

公开(公告)日：2009-03-05

申请号：US12202708

申请日：2008-09-02

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： H01L21/28 ,  G03F1/00

CPC分类号： G03F1/32 ,  H01L21/28035

摘要： According to an aspect of an embodiment, a method of manufacturing a photomask has forming a laminate over a transparent substrate, the laminate having a light-shielding layer and a hard mask layer, forming a negative resist layer over the laminate, exposing and developing the negative resist layer over the laminate to form a first resist pattern having a main pattern in a main exposure area surrounded by an outer area, etching the hard mask layer using the first resist pattern as an etching mask to form a hard mask pattern, removing the first resist pattern from the laminate; forming a positive resist layer covering the hard mask pattern over the transparent substrate, exposing and developing the positive resist layer to form a second resist pattern, the second resist pattern and a light-shielding pattern disposed in the outer area and forming an opening disclosing the hard mask pattern.

摘要翻译： 根据实施方式的一个方面，制造光掩模的方法在透明基板上形成层压体，该层压体具有遮光层和硬掩模层，在层叠体上形成负的抗蚀剂层，曝光和显影 负层抗蚀剂层，以形成在由外部区域围绕的主曝光区域中具有主图案的第一抗蚀剂图案，使用第一抗蚀剂图案蚀刻硬掩模层作为蚀刻掩模以形成硬掩模图案，去除 来自层压板的第一抗蚀剂图案; 在所述透明基板上形成覆盖所述硬掩模图案的正性抗蚀剂层，暴露并显影所述正性抗蚀剂层以形成第二抗蚀剂图案，所述第二抗蚀剂图案和设置在所述外部区域中的遮光图案形成开口， 硬掩模图案。

公开(公告)号：US20090052227A1

公开(公告)日：2009-02-26

申请号：US12118064

申请日：2008-05-09

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/06

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

公开(公告)号：US07420843B2

公开(公告)日：2008-09-02

申请号：US11512325

申请日：2006-08-30

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/32 ,  G11C2211/565

摘要： A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, a source line coupled to one end of the NAND cell unit, and a bit line coupled to the other end of the NAND cell unit, wherein the NAND cell unit is biased in a data write mode as follows: a write voltage Vpgm is applied to a control gate of a selected memory cell in the NAND cell unit; a channel-isolating voltage is applied to control gates of non-selected memory cells disposed on the source line side of the selected memory cell at intervals of a certain number of memory cells; and a write medium voltage Vm lower than Vpgm is applied to control gates of the remaining non-selected memory cells.

摘要翻译： 一种非易失性半导体存储器件，包括具有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，耦合到NAND单元单元的一端的源极线以及耦合到另一端的位线 的NAND单元单元，其中NAND单元单元以如下的数据写入模式被偏置：将写入电压Vpgm施加到NAND单元单元中所选存储单元的控制栅极; 以特定数量的存储单元的间隔将通道隔离电压施加到设置在所选存储单元的源极侧的未选择存储单元的栅极; 并且将低于Vpgm的写入介质电压Vm施加到剩余的未选择存储单元的控制栅极。

公开(公告)号：US07405975B2

公开(公告)日：2008-07-29

申请号：US11485483

申请日：2006-07-13

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3454 ,  G11C2211/5621

摘要： A threshold voltage read method of a nonvolatile semiconductor memory device is disclosed. The threshold voltage read method applies a first threshold voltage measuring read voltage to the word line with a selection gate kept in a nonconductive state and then makes the selection gate conductive to read out a threshold voltage of the first data at the time of reading out the threshold voltage of the first data. Then, it applies a second threshold voltage measuring read voltage to the word line with the selection gate kept in the conductive state to read out a threshold voltage of the second data at the time of reading out the threshold voltage of the second data.

摘要翻译： 公开了一种非易失性半导体存储器件的阈值电压读取方法。 阈值电压读取方法将第一阈值电压测量读取电压施加到字线，其中选择栅极保持在非导通状态，然后使选择栅极导通以读出第一数据的阈值电压 第一数据的阈值电压。 然后，在读出第二数据的阈值电压时，将选择栅极保持导通状态的第二阈值电压测量读取电压施加到字线，以读出第二数据的阈值电压。

公开(公告)号：US07313027B2

公开(公告)日：2007-12-25

申请号：US11295567

申请日：2005-12-07

申请人： Koji Hosono

发明人： Koji Hosono

IPC分类号： G11C11/34

CPC分类号： G11C16/12

摘要： A nonvolatile semiconductor memory device having a first circuit for selecting one from the plurality of blocks, the first circuit having a plurality of transistors connected to word lines connected to some of the nonvolatile memory cells and a second circuit for generating a first voltage V1, a second voltage V2 and a third voltage V3 (V3

摘要翻译： 一种非易失性半导体存储器件，具有用于从所述多个块中选择一个的第一电路，所述第一电路具有连接到连接到所述非易失存储单元的一些的字线的多个晶体管和用于产生第一电压V 1的第二电路， 第二电压V 2和第三电压V 3（V 3

公开(公告)号：US07184314B2

公开(公告)日：2007-02-27

申请号：US11145940

申请日：2005-06-07

申请人： Koji Hosono ,  Koichi Fukuda

发明人： Koji Hosono ,  Koichi Fukuda

IPC分类号： G11C11/34

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/26

摘要： A semiconductor memory device comprises a driver including a first resistor, and a control signal generator including a second resistor. A storage unit is employed to store adjustment data for setting a resistance of said second resistor at a designed resistance, which is specified based on the state of the control signal actually obtained when the resistance of the second resistor is set to a certain designed value. The storage unit is referred to for stored data to switch the second resistor to control the state of the control signal. In addition, the first resistor is switched to a resistance corresponding to the resistance of the second resistor.

摘要翻译： 半导体存储器件包括具有第一电阻器的驱动器和包括第二电阻器的控制信号发生器。 存储单元用于存储调整数据，用于根据当第二电阻器的电阻被设置为某个设计值时实际获得的控制信号的状态来指定设计的电阻来设定所述第二电阻器的电阻。 存储单元用于存储数据以切换第二电阻器以控制控制信号的状态。 此外，第一电阻器被切换到对应于第二电阻器的电阻的电阻。