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公开(公告)号：US08125019B2
公开(公告)日：2012-02-28
申请号：US11550450
申请日：2006-10-18
IPC分类号： H01L29/792
CPC分类号： H01L27/0635 , H01L21/8249 , H01L27/0802
摘要： An electrically programmable resistor is presented. In one embodiment, a resistor includes a doped body within a substrate; a trapped charge region adjacent to the resistor, the resistance of the resistor controlled by an amount of trapped charge in the trapped charge region.
摘要翻译： 提出了电可编程电阻器。 在一个实施例中，电阻器包括在衬底内的掺杂体; 与电阻器相邻的俘获电荷区域，电阻器被俘获电荷区域中被俘获电荷的量控制。
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22.发明申请公开(公告)号：US20110284280A1
公开(公告)日：2011-11-24
申请号：US13195255
申请日：2011-08-01
IPC分类号： H05K1/11
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译： 一种结构和方法。 该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测 通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。
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公开(公告)号：US07919830B2
公开(公告)日：2011-04-05
申请号：US12062262
申请日：2008-04-03
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
IPC分类号： H01L21/8222
CPC分类号： H01L29/41708 , H01L27/0629 , H01L27/0658 , H01L29/66272 , H01L29/7322 , H01L29/78
摘要： A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
摘要翻译： 一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。 可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。 该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。
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24.发明授权Structures including means for lateral current carrying capability improvement in semiconductor devices 有权结构包括用于半导体器件中横向电流承载能力改进的装置公开(公告)号：US07904868B2
公开(公告)日：2011-03-08
申请号：US11873711
申请日：2007-10-17
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： G06F17/50
CPC分类号： H01L21/76816 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。
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公开(公告)号：US20100210043A1
公开(公告)日：2010-08-19
申请号：US12371724
申请日：2009-02-16
申请人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
发明人： Qizhi Liu , Ping-Chuan Wang , Kimball M. Watson , Zhijian J. Yang
CPC分类号： H01L22/34 , H01L2924/3011
摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.
摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。
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26.发明申请公开(公告)号：US20080308940A1
公开(公告)日：2008-12-18
申请号：US12198196
申请日：2008-08-26
申请人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
发明人： Natalie Barbara Feilchenfeld , Zhong-Xiang He , Qizhi Liu , BethAnn Rainey , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/522
CPC分类号： H01L21/76838 , H01L21/8249 , H01L23/53228 , H01L23/53257 , H01L23/53295 , H01L27/0623 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.
摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。
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公开(公告)号：US08234606B2
公开(公告)日：2012-07-31
申请号：US13080716
申请日：2011-04-06
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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28.发明授权公开(公告)号：US08017514B2
公开(公告)日：2011-09-13
申请号：US12115056
申请日：2008-05-05
IPC分类号： H01L21/00
CPC分类号： H01L23/522 , H01L21/76849 , H01L21/76867 , H01L21/76888 , H01L23/53214 , H01L23/53238 , H01L23/53257 , H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
摘要翻译： 一种结构和方法。 该方法包括：在基板上形成电介质层; 在所述电介质层中形成导电的第一和第二布线，所述第一和第二布线的顶表面与所述电介质层的顶表面共面; 并且（i）在介电层的顶表面上形成导电的第三导线，并且在第一和第二导线的顶表面之上，第三线电连接第一和第二导线中的每一个，第三线不可检测 通过光学显微镜检查或（ii）在电介质层的顶表面和衬底之间形成导电的第三线，第三电线电接触第一和第二电线中的每一个，第三电线不能通过光学显微镜检测。
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公开(公告)号：US20110185330A1
公开(公告)日：2011-07-28
申请号：US13080716
申请日：2011-04-06
IPC分类号： G06F17/50
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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公开(公告)号：US07981732B2
公开(公告)日：2011-07-19
申请号：US12105366
申请日：2008-04-18
申请人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
发明人： Dinesh A. Badami , Tom C. Lee , Baozhen Li , Gerald Matusiewicz , William T. Motsiff , Christopher D. Muzzy , Kimball M. Watson , Jean E. Wynne
IPC分类号： H01L21/268
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/5254 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.
摘要翻译： 激光熔丝编程方法。 激光熔丝具有包括具有在暴露于激光束之后改变其电阻的特性的材料的熔断体。 激光束被引导到熔丝链，激光束被控制，使得响应于激光束对熔丝链的冲击，熔丝链的电阻改变，但是熔丝链不会被吹掉。
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