公开(公告)号：US20080076071A1

公开(公告)日：2008-03-27

申请号：US11588496

申请日：2006-10-28

Applicant: Seok-Hyun Lim ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Seung-Pil Chung ,  Dong-Seok Lee

Inventor： Seok-Hyun Lim ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Seung-Pil Chung ,  Dong-Seok Lee

IPC: G03F7/00

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

Abstract: First, second and third layers are formed on a substrate for forming a fine pattern. A first mask pattern having a first space is formed on the third layer. A third layer pattern having a second space exposing the second layer is formed. A first sacrificial layer is formed on the second layer having the third layer pattern. A fourth layer is formed on the first sacrificial layer. A double mask pattern including the first and second mask patterns is formed using the second mask pattern in the second space. A second sacrificial layer is formed on the first sacrificial layer. A sacrificial layer pattern having a third space is formed by removing the double mask pattern, the third layer pattern, and a portion of the first sacrificial layer. An insulation layer pattern is formed by removing a portion of the first and second layers.

Abstract translation: 首先，在用于形成精细图案的基板上形成第二和第三层。 具有第一空间的第一掩模图案形成在第三层上。 形成具有暴露第二层的第二空间的第三层图案。 在具有第三层图案的第二层上形成第一牺牲层。 在第一牺牲层上形成第四层。 使用第二空间中的第二掩模图案形成包括第一和第二掩模图案的双掩模图案。 在第一牺牲层上形成第二牺牲层。 通过去除双掩模图案，第三层图案和第一牺牲层的一部分来形成具有第三空间的牺牲层图案。 通过去除第一层和第二层的一部分来形成绝缘层图案。

公开(公告)号：US07226867B2

公开(公告)日：2007-06-05

申请号：US10419075

申请日：2003-04-21

Applicant: Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

Inventor： Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

IPC: H01L21/302

CPC classification number: C23F4/00 ,  H01L21/32136 ,  H01L21/32139

Abstract: Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Abstract translation: 提供了蚀刻金属层的方法和使用包括Cl 2 N 2和N 2 N的蚀刻气体的半导体器件的金属化方法。 在金属层上形成掩模层，将蚀刻气体供给到金属层，并使用掩模层作为蚀刻掩模，通过蚀刻气体蚀刻金属层。 金属层可以由铝或铝合金形成。 Cl 2 N 2和N 2可以1:1至1:10的比例混合。 蚀刻气体还可以包括另外的气体，例如包括元素H，O，F，He或C的惰性气体或气体。此外，N 2可以以 蚀刻气体总流量的45-65％，这导致半导体器件中的微负载和锥形缺陷的发生减少。

公开(公告)号：US07001817B2

公开(公告)日：2006-02-21

申请号：US10696417

申请日：2003-10-29

Applicant: Sang-Won Yeo ,  Jeong-Sic Jeon ,  Chang-Jin Kang ,  Chang-Won Lee

Inventor： Sang-Won Yeo ,  Jeong-Sic Jeon ,  Chang-Jin Kang ,  Chang-Won Lee

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28176 ,  H01L29/4941 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a gate electrode. A portion of the gate insulating film is removed to form an undercut region beneath the gate electrode. A buffer silicon film is formed over an entire surface of the resultant substrate to cover the gate electrode and to fill the undercut region. The buffer silicon film is selectively oxidized to form a buffer silicon oxide film.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底上形成栅极绝缘膜和栅极电极膜，以及对栅电极膜进行构图以形成栅电极。 去除栅极绝缘膜的一部分以在栅极电极下方形成底切区域。 在所得基板的整个表面上形成缓冲硅膜以覆盖栅电极并填充底切区域。 缓冲硅膜被选择性地氧化以形成缓冲氧化硅膜。

公开(公告)号：US20050158948A1

公开(公告)日：2005-07-21

申请号：US11058670

申请日：2005-02-15

Applicant: Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

Inventor： Myeong-Cheol Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Young Son

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

公开(公告)号：US20050130371A1

公开(公告)日：2005-06-16

申请号：US11048995

申请日：2005-02-02

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

公开(公告)号：US20050112819A1

公开(公告)日：2005-05-26

申请号：US10977385

申请日：2004-10-29

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-II Cho

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-II Cho

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract translation: 形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极， 电容器介电层位于第一和第二电容器电极之间。 更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

公开(公告)号：US06867096B2

公开(公告)日：2005-03-15

申请号：US10855165

申请日：2004-05-27

Applicant: Sung-IL Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-IL Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US08941165B2

公开(公告)日：2015-01-27

申请号：US12779300

申请日：2010-05-13

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/314 ,  H01L21/316

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US07709346B2

公开(公告)日：2010-05-04

申请号：US11624905

申请日：2007-01-19

Applicant: Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

Inventor： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC: H01L21/76

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract translation: 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07319255B2

公开(公告)日：2008-01-15

申请号：US11138034

申请日：2005-05-26

Applicant: Sung-Wook Hwang ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

Inventor： Sung-Wook Hwang ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC: H01L29/94 ,  H01L21/28

CPC classification number: H01L29/4236 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66621

Abstract: A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.

Abstract translation: 提供了包括晶体管及其形成方法的半导体器件。 半导体器件包括金属栅电极。 金属栅电极的下部填充形成在衬底的预定区域处的沟道沟槽，并且金属栅电极的上部在衬底上突出。 栅极绝缘层插入在沟道沟槽的内侧壁和底表面之间以及金属栅电极之间。 源极/漏极区域形成在金属栅电极两侧的衬底处。