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    CIRCUIT AND METHOD FOR ACCESSING A BIT CELL IN A SPIN-TORQUE MRAM
    21.
    发明申请
    CIRCUIT AND METHOD FOR ACCESSING A BIT CELL IN A SPIN-TORQUE MRAM 审中-公开
    用于接收转子MRAM中的位单元的电路和方法

    公开(公告)号：US20160042781A1

    公开(公告)日：2016-02-11

    申请号：US14918998

    申请日：2015-10-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693

    Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.

    Abstract translation: 用于调节施加到自旋转矩磁阻随机存取存储器（ST-MRAM）的磁阻位元的电压的电路和方法降低了字线晶体管的时间依赖介电击穿应力。 在读或写操作期间，根据正在执行的操作（写0，写1和读），仅将所选位单元的端部下拉至低电压和/或上拉至高电压。 未选择的位单元的端部保持在预充电电压，而在读取和写入操作期间单独定时的信号上拉或下拉所选位单元的端部。

    Self referencing sense amplifier for spin torque MRAM
    23.
    发明授权
    Self referencing sense amplifier for spin torque MRAM 有权
    用于自旋转矩MRAM的自参考读出放大器

    公开(公告)号：US09111622B2

    公开(公告)日：2015-08-18

    申请号：US13872993

    申请日：2013-04-29

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： Chitra K. Subramanian ,  Syed M. Alam

    IPC: G11C11/16

    CPC classification number: G11C11/1673

    Abstract: Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.

    Abstract translation: 电路和方法通过使用其在一个状态下的施加电压与相对恒定电阻的电阻变化的特性来提供电阻式存储器单元的自参考感测，而不管其相反状态下的施加电压如何。 基于具有均衡电阻的初始偏置状态，使用模拟位线和位线之间的第二偏置状态下的电流比较来确定存储器单元的状态，因为电流的显着差异意味着存储单元状态 具有显着的电阻系数。 施加到模拟位线的偏移电流可选地可以用于提供对称性和更大的感测余量。

    CIRCUIT AND METHOD FOR SPIN-TORQUE MRAM BIT LINE AND SOURCE LINE VOLTAGE REGULATION
    24.
    发明申请
    CIRCUIT AND METHOD FOR SPIN-TORQUE MRAM BIT LINE AND SOURCE LINE VOLTAGE REGULATION 审中-公开
    用于旋转扭矩MRAM位线和电源线电压调节的电路和方法

    公开(公告)号：US20150206570A1

    公开(公告)日：2015-07-23

    申请号：US14676100

    申请日：2015-04-01

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693

    Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.

    Abstract translation: 用于调节施加到自旋转矩磁阻随机存取存储器（ST-MRAM）的磁阻位元的电压的电路和方法降低了字线晶体管的时间依赖介电击穿应力。 在读或写操作期间，根据正在执行的操作（写0，写1和读），只有所选位单元的末端被拉低至低电压和/或上拉至高电压。 未选择的位单元的端部保持在预充电电压，而在读取和写入操作期间单独定时的信号上拉或下拉所选位单元的端部。

    Write driver circuit and method for writing to a spin-torque MRAM
    26.
    发明授权
    Write driver circuit and method for writing to a spin-torque MRAM 有权
    写入驱动电路和写入自旋转矩MRAM的方法

    公开(公告)号：US08929132B2

    公开(公告)日：2015-01-06

    申请号：US13679454

    申请日：2012-11-16

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

    Abstract: A write driver for writing to a spin-torque magnetoresistive random access memory (ST-MRAM) minimizes sub-threshold leakage of the unselected (off) word line select transistors in the selected column. An effective metal resistance in the bit line and/or source line is reduced and power supply noise immunity is increased. Write driver bias signals are isolated from global bias signals, and a first voltage is applied at one end of a bit line using one of a first NMOS-follower circuit or a first PMOS-follower circuit. A second voltage is applied at opposite ends of a source line using, respectively, second and third PMOS-follower circuits, or second and third NMOS-follower circuits.

    Abstract translation: 用于写入自旋扭矩磁阻随机存取存储器（ST-MRAM）的写入驱动器使选定列中未选择（关闭）字线选择晶体管的亚阈值泄漏最小化。 位线和/或源极线中的有效金属电阻降低，并且提供电源抗扰度。 写入驱动器偏置信号与全局偏置信号隔离，并且使用第一NMOS跟随器电路或第一PMOS跟随器电路之一在位线的一端施加第一电压。 分别使用第二和第三PMOS跟随器电路或第二和第三NMOS跟随器电路在源极线的相对端施加第二电压。

    RESPONSE TO TAMPER DETECTION IN A MEMORY DEVICE
    28.
    发明申请
    RESPONSE TO TAMPER DETECTION IN A MEMORY DEVICE 有权
    对存储器件中的篡改器检测的响应

    公开(公告)号：US20140230079A1

    公开(公告)日：2014-08-14

    申请号：US14175063

    申请日：2014-02-07

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G06F21/78

    CPC classification number: G06F21/79 ,  G06F3/062 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/78 ,  G06F21/86 ,  G06F2221/2143 ,  G11C7/24 ,  G11C11/1695

    Abstract: In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

    Abstract translation: 响应于篡改尝试指示，存储器设备选择性地禁用一个或多个存储器操作。 禁用可以通过不同的技术实现，包括改变与执行存储器操作相关联的偏置电压，选通执行存储器操作所需的电流，以及将所需电流限制在低于操作所需阈值幅度的幅度。 禁用内存操作后，可以生成模拟电流。 模拟电流旨在模拟在不被禁用时在存储器操作期间通常消耗的电流，从而导致用户认为即使正在尝试的存储器操作实际上不被执行，设备也继续正常地操作。

    Midpoint sensing reference generation for STT-MRAM
    30.
    发明授权
    Midpoint sensing reference generation for STT-MRAM 有权

    公开(公告)号：US12165684B2

    公开(公告)日：2024-12-10

    申请号：US18297793

    申请日：2023-04-10

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Yaojun Zhang ,  Frederick Neumeyer

    IPC: G11C11/16

    Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

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