Abstract:
A method of performing immersion lithography on a semiconductor wafer is provided. The method includes providing a layer of resist onto a surface of the semiconductor wafer. Next, an edge-bead removal process spins the wafer at a speed greater than 1000 revolutions per minute and dispenses solvent through a nozzle while the wafer is spinning. Then, the resist layer is exposed using an immersion lithography exposure system.
Abstract:
A method of creating a resist image on a semiconductor substrate includes exposing a layer of photoresist on the semiconductor substrate and developing the exposed layer of photoresist using a first fluid including supercritical carbon dioxide and a base such as Tetra-Methyl Ammonium Hydroxide (TMAH). Additionally, the developed photoresist can be cleaned using a second fluid including supercritical carbon dioxide and a solvent such as methanol, ethanol, isopropanol, and xylene.
Abstract:
A novel method for eliminating or reducing the accumulation of electrostatic charges on semiconductor wafers during spin-rinse-drying of the wafers is disclosed. The method includes rinsing a wafer; applying an ionic solution to the wafer; and spin-drying the wafer. During the spin-drying step, the ionic solution neutralizes electrostatic charges on the wafer as the wafer is rotated. This reduces the formation of defects in devices fabricated on the wafer, as well as prevents or reduces electrostatic interference with processing equipment during photolithographic and other fabrication processes.
Abstract:
A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.
Abstract:
A mask with extended mask window for forming patterns on a semiconductor substrate. The mask includes a main chip array having four sides for forming patterns of a main chip in a semiconductor substrate and a plurality of extended mask windows arranged around the main chip array. A method of dummy exposure using the mask includes providing a semiconductor substrate comprising a nitride layer with a plurality of main chip areas therein, and a plurality of unpatterned areas therein, forming a resist layer on the semiconductor substrate, providing an exposure mask comprising a main chip array and a plurality of extended mask windows, patterning the main chip areas of the semiconductor substrate using the main chip array of the exposure mask, patterning the unpatterned areas of the semiconductor substrate using the windows of the exposure mask, and removing the unexposed portions of the resist layer.
Abstract:
A method and system for cleaning lens used in an immersion lithography system is disclosed. After positioning a wafer in the immersion lithography system, a light exposing operation is performed on the wafer using an objective lens immersed in a first fluid containing surfactant, wherein the surfactant reduces a likelihood for having floating defects adhere to the wafer and the objective lens.
Abstract:
A method of fabricating a phase shift mask (PSM) is described. A patterned photoresist layer is formed on an opaque layer over a transparent plate. A thin mask layer is formed on the sidewalls of the patterned photoresist layer. The exposed opaque layer and transparent plate thereunder are then removed while using the patterned photoresist layer and mask layer as a mask. A phase shift opening is formed in the transparent plate, and thereby a phase shift layer is formed at the place where the phase shift opening is located. The patterned photoresist layer and the opaque layer thereunder are then removed to expose the transparent plate. The opaque layer under the mask layer can precisely self-align the phase shift layer to prevent alignment deviation caused by multiple lithography processes. The precision of the phase shift mask can be increased, and mask manufacture cost can be lowered.
Abstract:
A method of forming a feature pattern in a photosensitive layer includes forming the photosensitive layer on a substrate, providing a first mask having a first opaque area thereon, and performing a first exposure process with a first dose to form a first unexposed image in the photosensitive layer. The method further includes performing a second exposure process with a second dose to expose sidewalls of the first unexposed image so that the sidewalls of the first unexposed image receive at least a portion of the second dose thus forming a second unexposed image in the photosensitive layer, and developing the photosensitive layer with a developing process to form the feature pattern and to create features having smaller widths than those which would result in developing the photosensitive layer of the first unexposed image.
Abstract:
A method of forming holes in a layer through a cross-shape image exposure. The method includes removing a section from each corner of the rectangular patterns on a photomask to form cross-shape patterns so that circular or elliptical contact holes are formed on a photoresist layer after photo-exposure and development. Optical image contrast between contacts is increased by the cross-shape patterns on the photomask.
Abstract:
A stringer block is formed on the interface between a HDP silicon oxide layer and a silicon substrate. During an etching process for defining the profile of a floating gate, the stringer block functions to expose a bottom corner stringer. Following that, a polysilicon etching process effectively removes the bottom corner stringer. As a result, a stringerless flash memory cell is formed to prevent leakage currents, resulting from the bottom corner stringer, and improve both the reliability and data retention ability of the device.