公开(公告)号：US6144588A

公开(公告)日：2000-11-07

申请号：US150802

申请日：1998-09-10

Applicant: Federico Pio ,  Bruno Vajana ,  Paola Paruzzi

Inventor： Federico Pio ,  Bruno Vajana ,  Paola Paruzzi

IPC: G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C11/56 ,  G11C16/06 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C11/5621 ,  G11C16/30

Abstract: A generator for generating a plurality of predetermined voltage values for non-volatile memories. The generator includes an input node, a plurality of circuit branches, and an output terminal. The input node has a reference voltage and is connected to at least one of the circuit branches. Each of the circuit branches has at least one active element to selectively and independently turn on and turn off each of the circuit branches by a voltage applied to a control terminal of each active element. The output terminal connects to at least one of the circuit branches and supplies a voltage level based on the reference voltage and a voltage drop across each activated circuit branch. Alternatively, the output terminal supplies a floating voltage level in the event of one or more of the active elements along each of the circuit branches being turned off so as to isolate the input node from the output terminal.

Abstract translation: 一种用于为非易失性存储器产生多个预定电压值的发生器。 发生器包括输入节点，多个电路分支和输出端子。 输入节点具有参考电压并且连接到至少一个电路分支。 每个电路分支具有至少一个有源元件，以通过施加到每个有源元件的控制端子的电压来选择性地和独立地接通和关断每个电路分支。 输出端子连接到至少一个电路分支，并且基于参考电压提供电压电平，并且在每个激活的电路分支之间提供电压降。 或者，输出端子在沿着每个电路分支的一个或多个有源元件断开的情况下提供浮动电压电平，以将输入节点与输出端子隔离。

公开(公告)号：US6115313A

公开(公告)日：2000-09-05

申请号：US302231

申请日：1999-04-29

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C5/14 ,  G11C16/10 ,  G11C7/00

CPC classification number: G11C16/105 ,  G11C16/102 ,  G11C5/143

Abstract: A method for saving and restoring data in the event of unwanted interruption of programming, the control logic unit of the memory controls writing of the data that would otherwise be lost and its address, in an appropriate backup memory location. To this end, the backup memory location is maintained erased, such as to allow immediate writing of the data and its address, in case of interruption of programming. To guarantee functioning even in the absence of an external supply, appropriate charge accumulators are provided, which can guarantee availability of a write-only cycle. As soon as a voltage drop is detected, the operations in progress are interrupted, and the backup operations for the data being programmed are activated; when the memory is switched on again, it is verified whether an interruption of the writing cycle has previously occurred, and thus the data saved can be recovered into the main memory.

Abstract translation: 在编程不期望的中断的情况下保存和恢复数据的方法，存储器的控制逻辑单元控制在相应的备份存储器位置中将丢失的数据的写入及其地址。 为此，备份存储器位置被保持被擦除，例如在编程中断的情况下允许立即写入数据及其地址。 为了保证在没有外部电源的情况下运行，提供适当的电荷累加器，这样可以保证只写周期的可用性。 一旦检测到电压降，正在进行的操作被中断，并且正在编程的数据的备份操作被激活; 当存储器再次接通时，验证是否先前已经发生了写入周期的中断，从而可以将保存的数据恢复到主存储器中。

公开(公告)号：US5936298A

公开(公告)日：1999-08-10

申请号：US761185

申请日：1996-12-06

Applicant: Piero Capocelli ,  Raffaele Zambrano ,  Federico Pio ,  Carlo Riva

Inventor： Piero Capocelli ,  Raffaele Zambrano ,  Federico Pio ,  Carlo Riva

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L29/00

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H01L23/5227 ,  H01F2017/0086 ,  H01L2924/0002

Abstract: Inductive structures make highly efficient use of the magnetic flux generd, and are consistent with integrated circuit manufacturing techniques. The structures include electrically conductive layers and interconnecting conductor filled vias to define a helical winding surrounding a closed magnetic core. The magnetic core may also be formed by semiconductor manufacturing techinuqes. A method of making the structures on a semiconductor substrate concurrently with the formation of the integrated circuit itself is also disclosed.

Abstract translation: 感应结构高效地利用所产生的磁通量，并与集成电路制造技术保持一致。 这些结构包括导电层和互连导体填充的通孔，以限定围绕封闭磁芯的螺旋绕组。 磁芯也可以由半导体制造技术形成。 还公开了与形成集成电路本身同时在半导体衬底上制造结构的方法。

公开(公告)号：US5792670A

公开(公告)日：1998-08-11

申请号：US475671

申请日：1995-06-06

Applicant: Federico Pio ,  Carlo Riva

Inventor： Federico Pio ,  Carlo Riva

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

Abstract translation: 一种用于编程两电平多晶硅EEPROM存储单元的方法，该单元在半导体衬底上的MOS技术中实现，并且包括浮置栅晶体管和覆盖浮置栅极的其它控制栅极，其间具有介电层， 在单元写入阶段期间向控制栅极施加负电压。 这使得施加在薄隧道氧化物层上的电压被分布，以便减少“孔”的最大能量并提高氧化物的可靠性。 此外，通过在写入阶段期间控制到漏极区域的脉冲的上升速度以及在擦除阶段期间对控制栅极的脉冲的上升速度，可以设定流过隧道氧化物的最大电流并施加电场 隧道氧化物保持恒定，从而可延长设备使用寿命。

公开(公告)号：US5527728A

公开(公告)日：1996-06-18

申请号：US329309

申请日：1994-10-26

Applicant: Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

Inventor： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

Abstract translation: 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：US08759969B1

公开(公告)日：2014-06-24

申请号：US13346076

申请日：2012-01-09

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L23/04

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/67092

Abstract: In various embodiments, an integrated circuit die is provided. The integrated circuit die may include a circuit on a surface of a semiconductor substrate that has a peripheral sidewall extending substantially perpendicular to and away from the surface. A first protective layer may cover the sidewall of the semiconductor substrate and peripheral edges of the circuit to provide protection from contaminant diffusion. In some embodiments, a semiconductor substrate is provided that has a plurality of dice contained thereon. Each of the dice may have an integrated circuit region and a peripheral sidewall etched into the semiconductor substrate. A first protective layer may be used to cover the peripheral sidewall of the semiconductor substrate to provide protection from contaminant diffusion. Additional apparatuses, systems, and methods are disclosed.

Abstract translation: 在各种实施例中，提供集成电路管芯。 集成电路管芯可以包括在半导体衬底的表面上的电路，其具有基本上垂直于和远离表面延伸的周边侧壁。 第一保护层可以覆盖半导体衬底的侧壁和电路的外围边缘以提供防止污染物扩散的保护。 在一些实施例中，提供半导体衬底，其上包含多个裸片。 每个骰子可以具有蚀刻到半导体衬底中的集成电路区域和外围侧壁。 可以使用第一保护层来覆盖半导体衬底的周边侧壁以提供防止污染物扩散的保护。 公开了附加装置，系统和方法。

公开(公告)号：US20120096246A1

公开(公告)日：2012-04-19

申请号：US12904807

申请日：2010-10-14

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G06F12/06 ,  G06F12/02 ,  G06F9/38

CPC classification number: G06F12/0638 ,  G06F3/0611 ,  G06F3/0638 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/205

Abstract: Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.

Abstract translation: 非易失性存储包括具有不同读延迟的第一和第二存储器类型。 闪存和相变存储器是示例。 数据块的第一部分存储在相变存储器中，数据块的第二部分被存储在闪速存储器中。 在读取操作期间在数据块的第二部分之前访问数据块的第一部分。

公开(公告)号：US08093090B1

公开(公告)日：2012-01-10

申请号：US12577602

申请日：2009-10-12

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L21/00

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/67092

Abstract: In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped to a thickness smaller than the trench depth to separate the integrated circuit from other integrated circuits on the same substrate. Increased protection against contaminant diffusion into the integrated circuit through the sidewall at the periphery is obtained with one or more protective layers. The substrate area useful for integrated circuit fabrication is also increased.

Abstract translation: 在集成电路的制造中，沿着集成电路的周边形成具有侧壁的沟槽，并且将衬底回填至小于沟槽深度的厚度，以将集成电路与同一衬底上的其他集成电路分离 。 通过一个或多个保护层获得增强的防止通过外围侧壁污染物扩散到集成电路中的保护。 用于集成电路制造的衬底面积也增加。

公开(公告)号：US07601590B2

公开(公告)日：2009-10-13

申请号：US11033776

申请日：2005-01-12

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

Abstract translation: 电子存储器电路包括EEPROM存储器单元的矩阵。 每个存储单元包括MOS浮栅晶体管和选择晶体管。 矩阵包括多个行和列，每行具有字线，并且每列包括以线组组织的位线，以便以字节为单位对矩阵单元进行分组，每个矩阵单元具有关联的控制栅极线。 一对单元具有公共源极区域，并且相对于该公共源极区域对称地设置的每个单元具有公共控制栅极区域。

公开(公告)号：US20060164898A1

公开(公告)日：2006-07-27

申请号：US11318053

申请日：2005-12-23

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C7/02

CPC classification number: G11C29/026 ,  G11C7/14 ,  G11C16/04 ,  G11C16/28 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004

Abstract: In a semiconductor memory device, a method for obtaining at least one reference cell adapted to be exploited as a generator of a reference signal, the reference signal depending on a value of an electrical characteristic of the at least one reference cell. The method includes providing a population of auxiliary cells, operating on said population of auxiliary cells for varying a value of the electrical characteristic thereof, in such a way that the varied values are statistically distributed in a range including a value of the electrical characteristic corresponding to the reference signal, and choosing the at least one reference cell, wherein choosing includes choosing at least one auxiliary cell in the population of auxiliary cells having the value of the electrical characteristic close to the value corresponding to the reference signal with a pre-defined tolerance.