公开(公告)号：US6130839A

公开(公告)日：2000-10-10

申请号：US179738

申请日：1998-10-27

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  H01L21/336

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16

摘要： A flash memory comprises a plurality of word lines, a plurality of source lines and a plurality of bit lines, the word lines are arranged in a matrix with the bit lines and the source lines, respectively. Between every two adjacent bit line and source line and on every word line there forms a memory cell. Each bit line and source line are coupled to memory cells of two columns. During the procedure of "erase", two columns of memory cells can be erased at the same time. Methods of programming, erasing and reading the flash memory are much easy and controllable.

摘要翻译： 闪速存储器包括多个字线，多个源极线和多个位线，字线分别以位线和源极线排列成矩阵。 在每两个相邻位线和源极线之间以及每个字线上形成一个存储单元。 每个位线和源极线耦合到两列的存储单元。 在“擦除”过程中，可以同时擦除两列存储单元。 编程，擦除和读取闪存的方法很容易和可控。

公开(公告)号：US06107666A

公开(公告)日：2000-08-22

申请号：US53023

申请日：1998-04-01

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： G11C17/10 ,  H01L21/822 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/101 ,  G11C17/10 ,  H01L21/822

摘要： The method includes forming a first insulating layer over a substrate. A first metal layer is formed over the first insulating layer. The first metal layer is patterned to form a plurality of parallel bit lines. A second insulating layer is formed over the bit lines and first insulating layer. At least one via is formed in the second insulating layer. Tungsten fills the via to form a tungsten plug. A second metal layer is formed over the second insulating layer. The second metal layer is patterned to form a plurality of parallel word lines. The word lines and the bit lines crosses at an angle. The present invention is also directed toward a high density ROM device that comprises a substrate and at least one memory array, including a first insulating layer located over a surface of the substrate, and a bit line located on a surface of the first insulating layer. The memory array further includes a second insulating layer formed on a surface of the bit line, and at least one via is formed in the second insulating layer and is in communication with the bit line. Plural word lines are located on a surface of the second insulating layer. The bit lines and the word lines cross at an angle.

摘要翻译： 该方法包括在衬底上形成第一绝缘层。 在第一绝缘层上形成第一金属层。 图案化第一金属层以形成多个并行位线。 第二绝缘层形成在位线和第一绝缘层之上。 在第二绝缘层中形成至少一个通孔。 钨填充通孔以形成钨丝塞。 在第二绝缘层上形成第二金属层。 图案化第二金属层以形成多个平行字线。 字线和位线以一定角度交叉。 本发明还涉及一种高密度ROM器件，其包括衬底和至少一个存储器阵列，其包括位于衬底表面上的第一绝缘层和位于第一绝缘层的表面上的位线。 存储器阵列还包括形成在位线的表面上的第二绝缘层，并且至少一个通孔形成在第二绝缘层中并与位线连通。 多个字线位于第二绝缘层的表面上。 位线和字线以一定角度交叉。

公开(公告)号：US5926417A

公开(公告)日：1999-07-20

申请号：US965502

申请日：1997-11-06

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： G11C17/00 ,  G11C17/10 ,  G11C16/04

CPC分类号： G11C17/10 ,  G11C17/00

摘要： A read method for reading data from a ROM device is provided, which can be operated with a higher voltage to address the memory cells in the ROM device. The ROM device are formed with word and bit lines formed from metallization layers having a very low resistance so that the data current can be increased for increased performance. This read method is for use on a ROM device of the type including an array of memory cells formed at the intersections between a plurality of word lines and a plurality of bit lines. Of these memory cells, a first selected group are set to a permanently-ON state due to the forming of a contact window connecting the associated word line to the associated bit line, and a second selected group of the memory cells are set to a permanently-OFF state due to the forming of no contact window therein. The read method includes the steps of applying a high potential to the associated bit line of the currently addressed one of the memory cells while floating all of the other bit lines, and meanwhile applying a ground potential to the associated word line of the currently addressed one of the memory cells while floating all of the other word lines.

摘要翻译： 提供了一种用于从ROM装置读取数据的读取方法，其可以以更高的电压操作以对ROM装置中的存储器单元寻址。 ROM器件形成有由具有非常低电阻的金属化层形成的字和位线，使得可以增加数据电流以增加性能。 该读取方法用于包括形成在多个字线和多个位线之间的交叉处的存储单元阵列的类型的ROM器件。 在这些存储单元中，由于形成将相关联的字线连接到相关联的位线的接触窗口，将第一选定组设置为永久接通状态，并且将第二选定组的存储器单元设置为永久地 由于在其中形成没有接触窗口的-OFF状态。 读取方法包括以下步骤：在浮动所有其它位线时将高电位施加到当前寻址的存储单元的相关位线，同时将地电位施加到当前寻址的一个的相关字线 的存储单元，同时浮动所有其他字线。

公开(公告)号：US5877049A

公开(公告)日：1999-03-02

申请号：US717981

申请日：1996-09-23

申请人： Yowjuang W. Liu ,  Kuang-Yeh Chang

发明人： Yowjuang W. Liu ,  Kuang-Yeh Chang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7832 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/6659 ,  Y10S257/901

摘要： A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

摘要翻译： 通过改善短沟道控制来提高器件缩放的新型MOS晶体管结构包括在MOS晶体管的沟道区下面的掩埋后栅极。 与通过电气传递到掩埋后门的阱的单独接触改善了短通道控制而没有性能下降。 在优选实施例中，当关闭n沟道MOS晶体管时，背栅极接地。 在替代实施例中，掩埋层产生逆行p阱。 在一些应用中，可以使用多个掩埋层，其中一个或多个是平面的。 CMOS器件可能具有独立的多重埋后栅。

公开(公告)号：US5874339A

公开(公告)日：1999-02-23

申请号：US808257

申请日：1997-02-28

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L21/8246

CPC分类号： H01L27/1021 ,  H01L21/8229

摘要： A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon nitride layer is over the N well. A field oxide layer is formed over the substrate. The silicon nitride layer is removed. The N well is doped using first P-type ions to form a plurality of essentially parallel P-pole regions. An insulating layer is formed over the field oxide layer. A plurality of contact windows are formed within the insulating layer to expose a portion of the P-pole regions. The N well is doped and annealed, to form a plurality of P-type diffusion regions under the exposed portions of the P-pole regions. The P-pole regions are doped and annealed, to form a plurality of N-type diffusion regions in the exposed portions of the P-pole regions. A metal layer is formed which fills the contact windows. The metal layer is patterned to form a plurality of essentially parallel word lines. A read only memory device is proposed that includes as plurality of essentially parallel P-pole regions are located on a substrate. A plurality of P-type diffusion regions are located under selected portions of respective P-pole regions. A plurality of N-type diffusion regions are located over respective selected portions of the P-pole regions. Each respective N-type diffusion region and associated P-pole region forms a diode.

摘要翻译： 形成ROM的方法包括在P型衬底上形成衬垫氧化层，在衬垫氧化层上形成氮化硅层并对氮化硅层进行构图。 在P型衬底中形成N阱，其中一些氮化硅层在N阱之上。 在衬底上形成场氧化物层。 去除氮化硅层。 使用第一P型离子掺杂N阱以形成多个基本上平行的P极区域。 在场氧化物层上形成绝缘层。 在绝缘层内形成多个接触窗，露出一部分P极区域。 N阱被掺杂并退火，以在P极区域的暴露部分之下形成多个P型扩散区域。 P极区域被掺杂并退火，以在P极区域的暴露部分中形成多个N型扩散区域。 形成填充接触窗的金属层。 将金属层图案化以形成多个基本平行的字线。 提出了一种只读存储器件，其包括多个基本上平行的P极区域位于衬底上。 多个P型扩散区域位于相应P极区域的选定部分的下方。 多个N型扩散区域位于P极区域的各个选定部分上。 每个相应的N型扩散区和相关的P极区形成二极管。

公开(公告)号：US5554562A

公开(公告)日：1996-09-10

申请号：US417572

申请日：1995-04-06

申请人： Kuang-Yeh Chang ,  Yowjuang W. Liu ,  Mark I. Gardner ,  Frederick N. Hause

发明人： Kuang-Yeh Chang ,  Yowjuang W. Liu ,  Mark I. Gardner ,  Frederick N. Hause

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76294

摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

公开(公告)号：US5512506A

公开(公告)日：1996-04-30

申请号：US417568

申请日：1995-04-06

申请人： Kuang-Yeh Chang ,  Mark I. Gardner ,  Frederick N. Hause

发明人： Kuang-Yeh Chang ,  Mark I. Gardner ,  Frederick N. Hause

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/6659 ,  H01L29/7833

摘要： After growth of a thin oxide on a silicon semiconductor body, and formation of a gate thereover, a blanket layer of oxide is deposited over the resulting structure, this oxide layer having, as measured from the surface of the silicon body, relatively thick regions adjacent the sides of the gate and relatively thin regions extending therefrom. Upon implant of ions, the relatively thick regions block ions from passing therethrough into the semiconductor body, while the relatively thin regions allow passage of ions therethrough into the body. After drivein of the ions, the thick layer of oxide is isotopically etched to take a substantially uniform layer therefrom over the entire surface of the thick oxide layer, so that the thick regions thereof are reduced in width. Upon a subsequent ion implant step, the thick regions, now reduced in width from the sides of the gate, block passage of ions therethrough, while the thin regions allow ions therethrough into the silicon body. This process may be continued as chosen to from a desired source and drain profile.

摘要翻译： 在硅半导体本体上生长薄氧化物并在其上形成栅极之后，在所得结构上沉积氧化物覆盖层，该氧化物层具有从硅体表面测量的较厚的相邻区域 门的侧面和从其延伸的相对薄的区域。 在离子注入时，相对较厚的区域阻止离子通过其进入半导体本体，而较薄的区域允许离子通过其进入体内。 在离子的驱动之后，厚厚的氧化物层被同位素蚀刻以在厚氧化物层的整个表面上从其中获得基本均匀的层，使得其厚的区域的宽度减小。 在随后的离子注入步骤中，现在从栅极的侧面减小宽度的厚区域阻止离子通过其中，而薄区域允许离子通过其进入硅体。 该过程可以根据期望的源和漏极曲线选择继续。

公开(公告)号：US5427979A

公开(公告)日：1995-06-27

申请号：US138298

申请日：1993-10-18

申请人： Kuang-Yeh Chang

发明人： Kuang-Yeh Chang

IPC分类号： H01L23/525 ,  H01L21/441

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other. A method for making a multilevel antifuse structure in accordance with the present invention includes the steps of forming a first antifuse structure over a substrate, and forming a second antifuse structure over the first antifuse structure. In one embodiment, the first antifuse structure and the second antifuse structure are vertically aligned, and are interconnected in parallel. The parallel interconnection is preferably accomplished by tungsten vias formed by either a blanket tungsten deposition and subsequent etch-back, or by a selective tungsten deposition.

摘要翻译： 一种多层反熔丝结构，其特征在于基板，形成在基板上方的第一反熔丝结构，以及形成在第一反熔丝结构之上的第二反熔丝结构。 第一反熔丝结构优选地包括第一导电层，设置在第一导电层上的第一反熔丝层，设置在第一反熔丝层之上并设置有第一通孔的第一介电层，以及形成在第一通孔内的第一导电通孔 孔。 第二反熔丝结构优选地包括第二导电层，设置在第二导电层上的第二反熔丝层，设置在第二反熔丝层之上并设置有第二通孔的第二介电层，以及形成在第二通孔内的第二导电通孔 孔。 优选地，第一反熔丝层和第二反熔丝层被图案化成多个相对于彼此垂直对准或垂直交错的反熔丝区域。 根据本发明的制造多层反熔丝结构的方法包括以下步骤：在衬底上形成第一反熔丝结构，并在第一反熔丝结构上形成第二反熔丝结构。 在一个实施例中，第一反熔丝结构和第二反熔丝结构垂直对准，并联并联。 平行互连优选通过由覆盖钨沉积和随后的回蚀或通过选择性钨沉积形成的钨通孔来实现。

公开(公告)号：US5374833A

公开(公告)日：1994-12-20

申请号：US775085

申请日：1991-10-11

申请人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

发明人： Subhash R. Nariani ,  Vivek Jain ,  Dipankar Pramanik ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/532 ,  H01L27/115 ,  H02L45/00

CPC分类号： H01L23/291 ,  H01L21/314 ,  H01L23/298 ,  H01L23/5329 ,  H01L27/115 ,  H01L2924/0002 ,  Y10S438/91 ,  Y10S438/958

摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

摘要翻译： 本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。 非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

公开(公告)号：US5328865A

公开(公告)日：1994-07-12

申请号：US11084

申请日：1993-01-29

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

摘要： A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

摘要翻译： 一种制造抗熔丝结构的方法，其特征在于形成导电基层的步骤; 在基层上形成抗熔丝层; 图案化抗熔丝层以形成抗熔丝岛; 在反熔丝岛上形成绝缘层; 形成通过所述绝缘层到所述反熔丝岛的通孔; 在所述绝缘层上并在所述通孔内形成导电连接层; 以及图案化所述导电连接层以形成与所述反熔丝岛的导电接触。 优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。