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    Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information
    22.
    再颁专利
    Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information 有权
    通过用相应的操作码和开始信息以单独的单词传送低阶和高阶存储器地址位来传送数据的方法

    公开(公告)号：USRE39879E1

    公开(公告)日：2007-10-09

    申请号：US09559835

    申请日：2000-04-26

    申请人： Richard M. Barth ,  Matthew M. Griffin ,  Frederick A. Ware ,  Mark A. Horowitz

    发明人： Richard M. Barth ,  Matthew M. Griffin ,  Frederick A. Ware ,  Mark A. Horowitz

    IPC分类号： G06F12/02

    CPC分类号： G06F13/161 ,  G06F13/376

    摘要： A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten multiplexed transmission lines, identified as BusCtl and BusData [8:0]. The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible. The type of memory access is arranged over a plurality of clock cycles, placing the more critical bits first. The count of blocks of data requested is arranged to minimize the number of bit positions in the packet used and therefore the number of transmission lines of the bus and the number of bus receiver contacts on the receiving device.

    摘要翻译： 一种高速总线系统，其中至少一个主设备，例如处理器和至少一个DRAM从设备耦合到总线。 提供了一种创新的分组格式和设备接口，其利用多个时间和空间节省特征来减少设备接收机的管芯尺寸并降低总线上的总延迟。 在优选实施例中，请求分组在被标识为BusCt1和BusData [8：0]的十个多路复用传输线上传输。 分组在六个连续的总线周期上传输，其中在每个总线周期期间，发送分组的不同部分。 低位地址位在存储器请求的高位地址位之前移动。 这使得接收设备能够更快地处理存储器请求，因为可以立即确定关于先前参考的存储器参考的位置，并且可以尽可能快地启动DRAM上的页面模式访问。 存储器访问的类型被布置在多个时钟周期中，首先放置更关键的位。 所请求的数据块的计数被设置为使得所使用的分组中的比特位置的数量最小化，因此最小化总线的传输线的数量和接收设备上的总线接收器接触的数量。

    Rambus DRAM (RDRAM) apparatus and method for performing refresh operations
    23.
    发明授权
    Rambus DRAM (RDRAM) apparatus and method for performing refresh operations 失效
    用于执行刷新操作的DRAM装置和方法

    公开(公告)号：US06310814B1

    公开(公告)日：2001-10-30

    申请号：US09637892

    申请日：2000-08-08

    申请人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

    发明人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.

    摘要翻译： 一种用于在动态随机存取存储器（DRAM）组件中同时刷新第一和第二行存储器单元的装置和方法，所述动态随机存取存储器（DRAM）组件包括以行为单位组织的多组存储器单元。 DRAM组件中的命令接口接收激活请求和预充电请求。 DRAM组件中的行寄存器表示DRAM组件中的一行。 DRAM组件中的逻辑响应于激活请求而激活由行寄存器指示的行，并且响应于预充电请求预先充电该行，该行位于由激活请求指示的存储体中以及通过预充电请求。

    Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
    24.
    发明授权
    Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain 失效
    通过调整读取域来初始化动态随机存取存储器（DRAM）设备的方法和装置

    公开(公告)号：US6154821A

    公开(公告)日：2000-11-28

    申请号：US38358

    申请日：1998-03-10

    申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/00

    CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C7/20 ,  G11C8/12 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02B60/1235

    摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

    摘要翻译： 提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。 确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。 随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。 然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。 在确定每个DRAM器件的响应时间并且使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合 总线等于最长响应时间。 通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

    Apparatus and method for bus timing compensation
    28.
    发明授权
    Apparatus and method for bus timing compensation 有权
    总线定时补偿的装置和方法

    公开(公告)号：US06226757B1

    公开(公告)日：2001-05-01

    申请号：US09169245

    申请日：1998-10-09

    申请人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

    发明人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar ,  Thomas J. Holman ,  Andrew V. Anderson ,  Peter D. MacWilliams

    IPC分类号： G06F104

    CPC分类号： G06F13/4226

    摘要： A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.

    摘要翻译： 一个数字系统包括一个带有时钟信号的时钟线和一个具有比时钟信号周期长的信号时间的通信总线。 主设备连接到通信总线和时钟线。 主设备选择性地向通信总线施加信号。 一组从设备连接到通信总线和时钟线。 一组从设备的每个从设备具有由其在通信总线上的位置产生的相关联的延迟延迟。 每个从设备包括延迟电路以补偿相关联的延迟延迟，使得主设备响应于向通信总线应用信号而观察到每个从设备的均匀最小等待时间。