公开(公告)号：US5337285A

公开(公告)日：1994-08-09

申请号：US65804

申请日：1993-05-21

申请人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Matthew M. Griffin ,  Richard M. Barth ,  Mark A. Horowitz

发明人： Frederick A. Ware ,  James A. Gasbarro ,  John B. Dillon ,  Matthew M. Griffin ,  Richard M. Barth ,  Mark A. Horowitz

IPC分类号： G06F1/32 ,  G11C5/14 ,  H03K19/00 ,  H03K19/0175 ,  G11C7/00

CPC分类号： G11C5/14

摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.

摘要翻译： 电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。 锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。 提供备用锁存器来控制对组件的时钟输入。 在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。 因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以很小的延迟打开部件。

公开(公告)号：USRE39879E1

公开(公告)日：2007-10-09

申请号：US09559835

申请日：2000-04-26

申请人： Richard M. Barth ,  Matthew M. Griffin ,  Frederick A. Ware ,  Mark A. Horowitz

发明人： Richard M. Barth ,  Matthew M. Griffin ,  Frederick A. Ware ,  Mark A. Horowitz

IPC分类号： G06F12/02

CPC分类号： G06F13/161 ,  G06F13/376

摘要： A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten multiplexed transmission lines, identified as BusCtl and BusData [8:0]. The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible. The type of memory access is arranged over a plurality of clock cycles, placing the more critical bits first. The count of blocks of data requested is arranged to minimize the number of bit positions in the packet used and therefore the number of transmission lines of the bus and the number of bus receiver contacts on the receiving device.

摘要翻译： 一种高速总线系统，其中至少一个主设备，例如处理器和至少一个DRAM从设备耦合到总线。 提供了一种创新的分组格式和设备接口，其利用多个时间和空间节省特征来减少设备接收机的管芯尺寸并降低总线上的总延迟。 在优选实施例中，请求分组在被标识为BusCt1和BusData [8：0]的十个多路复用传输线上传输。 分组在六个连续的总线周期上传输，其中在每个总线周期期间，发送分组的不同部分。 低位地址位在存储器请求的高位地址位之前移动。 这使得接收设备能够更快地处理存储器请求，因为可以立即确定关于先前参考的存储器参考的位置，并且可以尽可能快地启动DRAM上的页面模式访问。 存储器访问的类型被布置在多个时钟周期中，首先放置更关键的位。 所请求的数据块的计数被设置为使得所使用的分组中的比特位置的数量最小化，因此最小化总线的传输线的数量和接收设备上的总线接收器接触的数量。

公开(公告)号：US06718431B2

公开(公告)日：2004-04-06

申请号：US10053632

申请日：2002-01-18

申请人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon

发明人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

摘要翻译： 存储器设备具有构成流水线阶段的接口电路和存储器核心，每个阶段是与存储器核心相关联的通用序列中的步骤。 存储装置具有多个操作单元，例如预充电，感测，读取和写入，其处理操作单元耦合到的存储器核的原始操作。 存储装置还包括多个传输单元，其被配置为从外部连接获取信息，指定操作单元之一的操作并且在存储器核心和外部连接之间传送数据。 运输单元与运营单元同时运行作为流水线的附加阶段，从而创建一种在普通应用的存储器参考流下以高吞吐量和低服务时间运行的存储器件。

公开(公告)号：US06356975B1

公开(公告)日：2002-03-12

申请号：US09169526

申请日：1998-10-09

申请人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon ,  by Nancy David Dillon

发明人： Richard M. Barth ,  Ely K. Tsern ,  Mark A. Horowitz ,  Donald C. Stark ,  Craig E. Hampel ,  Frederick A. Ware ,  John B. Dillon ,  by Nancy David Dillon

IPC分类号： G06F1200

CPC分类号： G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

公开(公告)号：US08127152B2

公开(公告)日：2012-02-28

申请号：US10993046

申请日：2004-11-19

申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

IPC分类号： G06F1/00 ,  G06F13/00

CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02D10/151

摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

摘要翻译： 在实施例中提供了存储器件和系统的操作方法。 初始化操作在初始化序列期间以第一操作频率进行。 然后在第二操作频率下执行存储器存取操作。 第二个操作频率高于第一个操作频率。 此外，存储器访问操作包括读取操作和写入操作。 在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

公开(公告)号：US20120005437A1

公开(公告)日：2012-01-05

申请号：US13230741

申请日：2011-09-12

申请人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

发明人： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

摘要翻译： 存储器控制器具有在第一组互连资源上传送指定激活一行存储器单元的第一命令的接口，指定针对存储器单元行的写操作的第二命令，指定 是否与写入操作相关地进行预充电，指定是否将与写入操作相关联地发布数据掩码信息的代码，以及如果代码指定将发出数据掩码信息的数据掩码信息，指定是否选择性地 写入与写入操作相关联的写入数据的部分。 存储器控制器接口还通过第二组互连资源与第一组互连资源（写入数据）分离。

公开(公告)号：US07574616B2

公开(公告)日：2009-08-11

申请号：US10944320

申请日：2004-09-17

申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

IPC分类号： G06F1/26

CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02D10/151

摘要： A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.

摘要翻译： 在一个实施例中，提供了一种包括存储器单元阵列的存储器件以及用于存储表示在从掉电模式恢复之前存储器件准备好接收命令之前经过一段时间的值的寄存器电路。 该命令指定对存储单元阵列的访问。 延迟锁定环路电路使用外部时钟信号同步数据传输。 延迟锁定环路电路在一段时间内重新获得与外部时钟信号的同步。

公开(公告)号：US06226754B1

公开(公告)日：2001-05-01

申请号：US09169687

申请日：1998-10-09

申请人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar

发明人： Frederick A. Ware ,  Richard M. Barth ,  Donald C. Stark ,  Craig E. Hampel ,  Ely K. Tsern ,  Abhijit M. Abhyankar

IPC分类号： G06F104

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.

摘要翻译： 具有设备定时约束的电子设备包括耦合到承载行和列命令的互连结构的一组连接。 内存核心存储数据。 存储器接口连接到一组连接和存储器核心。 存储器接口包括用于根据行命令和列命令产生存储器核心定时信号的电路。 存储器核心定时信号具有时序约束，以确保正确的存储器核心操作。 存储器接口电路包括用于调整存储器核心定时信号的选定定时信号的定时的各个延迟部件。

公开(公告)号：US5680361A

公开(公告)日：1997-10-21

申请号：US389561

申请日：1995-02-14

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy Wayne Garrett, Jr. ,  John Girdner Atwood, Jr. ,  Michael P. Farmwald ,  Richard DeWitt Crisp

IPC分类号： G11C7/10 ,  G11C11/401

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/103 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

摘要翻译： 提供附加模式以增强存储器系统的功能和性能。 在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。 在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。 位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。 在另一个实施例中，提供单独的位掩码和字节掩码。 字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。 该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。 为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。 在计算机图形系统中，用于在前景和背景颜色之间进行选择。 该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

公开(公告)号：US5430676A

公开(公告)日：1995-07-04

申请号：US202290

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F12/00

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.