公开(公告)号：US20210288180A1

公开(公告)日：2021-09-16

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11069772B2

公开(公告)日：2021-07-20

申请号：US16221034

申请日：2018-12-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

公开(公告)号：US20190088479A1

公开(公告)日：2019-03-21

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/36 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US20170278924A1

公开(公告)日：2017-09-28

申请号：US15077579

申请日：2016-03-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  Reza Ghandi

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/808 ,  H01L29/73 ,  H01L29/78 ,  H01L29/16 ,  H01L29/861

CPC classification number: H01L29/0634 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66272 ,  H01L29/66909 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

公开(公告)号：US09601332B2

公开(公告)日：2017-03-21

申请号：US14986922

申请日：2016-01-04

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Zachary Matthew Stum ,  Reza Ghandi

IPC: H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L23/544 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L23/522 ,  H01L29/808

CPC classification number: H01L29/7802 ,  H01L21/02697 ,  H01L21/0485 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L23/5226 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/808 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

公开(公告)号：US20160380059A1

公开(公告)日：2016-12-29

申请号：US14752446

申请日：2015-06-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L29/0634 ,  H01L29/6606 ,  H01L29/8083 ,  H01L29/872

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

Abstract translation: 本文公开的主题涉及碳化硅（SiC）功率器件，更具体地，涉及用于SiC超结（SJ）功率器件的有源区域设计。 SiC-SJ器件包括具有一个或多个电荷平衡（CB）层的有源区。 每个CB层包括具有第一导电类型的半导体层和设置在半导体层的表面中的具有第二导电类型的多个浮动区域。 当将反向偏压施加到SiC-SJ器件时，多个浮动区域和半导体层都被配置为基本上耗尽以提供基本相等量的电离掺杂剂的电荷。

公开(公告)号：US12191384B2

公开(公告)日：2025-01-07

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11764257B2

公开(公告)日：2023-09-19

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US20230020337A1

公开(公告)日：2023-01-19

申请号：US17949325

申请日：2022-09-21

Applicant: General Electric Company

Inventor： Cheng-Po Chen ,  Reza Ghandi ,  David Richard Esler ,  David Mulford Shaddock ,  Emad Andarawis Andarawis ,  Liang Yin

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/532 ,  H01L21/02

Abstract: An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

公开(公告)号：US11056586B2

公开(公告)日：2021-07-06

申请号：US16147216

申请日：2018-09-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almem Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.