公开(公告)号：US20140167068A1

公开(公告)日：2014-06-19

申请号：US13718031

申请日：2012-12-18

申请人： GENERAL ELECTRIC COMPANY

发明人： Zachary Matthew Stum ,  Reza Ghandi

IPC分类号： H01L29/16 ,  H01L21/02

CPC分类号： H01L29/7802 ,  H01L21/02697 ,  H01L21/0485 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L23/5226 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/808 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

摘要翻译： 提出了一种碳化硅器件，其包括设置在碳化硅衬底的一部分上的栅电极以及设置在栅电极上的电介质膜。 该器件具有设置在栅电极附近的接触区域，并且具有设置在电介质膜上方并且在接触区域上方的层。 该层包括设置在电介质膜上的部分的镍，并且包括设置在接触区域上的部分的硅化镍。 镍硅化物层被配置为向碳化硅器件的接触区域提供欧姆接触。

公开(公告)号：US10903330B2

公开(公告)日：2021-01-26

申请号：US14091622

申请日：2013-11-27

申请人： General Electric Company

发明人： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L21/3213 ,  H01L21/027

摘要： The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

公开(公告)号：US20160307997A1

公开(公告)日：2016-10-20

申请号：US15194774

申请日：2016-06-28

申请人： GENERAL ELECTRIC COMPANY

发明人： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Motocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljuibisa Dragolijub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/861 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/36 ,  H01L21/04

CPC分类号： H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

摘要： A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.

摘要翻译： 半导体器件可以包括包含碳化硅的衬底; 设置在掺杂有第一掺杂剂类型的衬底上的漂移层; 邻近所述漂移层设置的阳极区域，其中所述阳极区域掺杂有第二掺杂剂类型; 以及连接终端延伸部，其邻近所述阳极区域设置并且围绕所述阳极区域延伸，其中所述连接终端延伸部具有宽度并且包括在第一方向和第二方向上分离的多个离散区域，并且以 第二掺杂剂类型，以便具有通常沿着远离主阻塞结的边缘的方向减小的功能形式的第二导电类型的有效掺杂分布。

公开(公告)号：US09406762B2

公开(公告)日：2016-08-02

申请号：US14396852

申请日：2013-05-15

申请人： GENERAL ELECTRIC COMPANY

发明人： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC分类号： H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

摘要： A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

摘要翻译： 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。

公开(公告)号：US20130126971A1

公开(公告)日：2013-05-23

申请号：US13740758

申请日：2013-01-14

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Micah Sandvik ,  Zachary Matthew Stum ,  Peter Almren Losee ,  James Jay McMahon

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

摘要： In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

摘要翻译： 在一个实施例中，本发明包括一个包含单个MOSFET单元的MOSFET。 每个单元包括形成在井内的U形孔（P型）和两个平行的源（N型）。 在多个位置连接多个源极（掺杂N）源极。 两个梯级之间的区域包括一个主体（P型）。 这些特征形成在形成在N型衬底上的N型外延层上。 联系人跨越并接触许多源级和身体。 栅极氧化物和栅极接触覆盖第一阱的支腿和第二相邻阱的支路，响应于栅极电压而反转导电性。 MOSFET包括多个这些单元以获得期望的低通道电阻。 在制造过程的几个状态下使用自对准技术形成单元区域。

公开(公告)号：US09601332B2

公开(公告)日：2017-03-21

申请号：US14986922

申请日：2016-01-04

申请人： GENERAL ELECTRIC COMPANY

发明人： Zachary Matthew Stum ,  Reza Ghandi

IPC分类号： H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L23/544 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L23/522 ,  H01L29/808

CPC分类号： H01L29/7802 ,  H01L21/02697 ,  H01L21/0485 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L23/5226 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/808 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

公开(公告)号：US20150144960A1

公开(公告)日：2015-05-28

申请号：US14091622

申请日：2013-11-27

申请人： General Electric Company

发明人： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/4933 ,  H01L21/0273 ,  H01L21/049 ,  H01L21/32139 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7802

摘要： The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

摘要翻译： 本文公开的主题涉及诸如碳化硅（SiC）功率器件（例如，MOSFET，IGBT等）的金属氧化物半导体（MOS）器件。在一个实施例中，半导体器件包括设置在 半导体层顶部。 半导体器件还包括具有锥形侧壁的栅电极。 此外，栅极包括设置在栅极氧化物层的顶部上的多晶硅层和设置在多晶硅层顶部的金属硅化物层。

公开(公告)号：US20130334612A1

公开(公告)日：2013-12-19

申请号：US13965437

申请日：2013-08-13

申请人： GENERAL ELECTRIC COMPANY

发明人： Cheng-Po Chen ,  Emad Andarawis Andarawis ,  Vinayak Tilak ,  Zachary Matthew Stum

IPC分类号： H01L29/06

CPC分类号： H01L29/0649 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/8213 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/8252

摘要： An integrated circuit includes a plurality of transistors. Each transistor is associated with a corresponding body terminal. At least one transistor is reverse biased at a first voltage level, and at least one other transistor is reverse biased at a second voltage level that is different from the first voltage level. Each body terminal is electrically isolated from every other body terminal via an isolation barrier. A transistor that is reverse biased at the first voltage level is electrically connected to a transistor that is reverse biased at the second voltage level, such that the electrically connected transistors operate to interact with each other while the respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit.

摘要翻译： 集成电路包括多个晶体管。 每个晶体管与相应的主体端子相关联。 至少一个晶体管以第一电压电平被反向偏置，并且至少一个其它晶体管被反向偏置在不同于第一电压电平的第二电压电平。 每个身体终端通过隔离屏障与每个其他身体终端电隔离。 在第一电压电平处被反向偏置的晶体管电连接到在第二电压电平处被反向偏置的晶体管，使得电连接的晶体管彼此相互作用，同时相应的体电压电平彼此不同 并且在集成电路的操作期间彼此独立地改变。

公开(公告)号：US09230807B2

公开(公告)日：2016-01-05

申请号：US13718031

申请日：2012-12-18

申请人： General Electric Company

发明人： Zachary Matthew Stum ,  Reza Ghandi

IPC分类号： H01L21/02 ,  H01L21/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L21/02697 ,  H01L21/0485 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L23/5226 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/808 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

摘要翻译： 提出了一种碳化硅器件，其包括设置在碳化硅衬底的一部分上的栅电极以及设置在栅电极上的电介质膜。 该器件具有设置在栅电极附近的接触区域，并且具有设置在电介质膜上方并且在接触区域上方的层。 该层包括设置在电介质膜上的部分的镍，并且包括设置在接触区域上的部分的硅化镍。 镍硅化物层被配置为向碳化硅器件的接触区域提供欧姆接触。

公开(公告)号：US20150236151A1

公开(公告)日：2015-08-20

申请号：US14182765

申请日：2014-02-18

申请人： GENERAL ELECTRIC COMPANY

发明人： James Jay McMahon ,  Ljubisa Dragoljub Stevanovic ,  Stephen Daley Arthur ,  Thomas Bert Gorczyca ,  Richard Alfred Beaupre ,  Zachary Matthew Stum ,  Alexander Viktorovich Bolotnikov

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/16

CPC分类号： H01L29/7827 ,  H01L21/045 ,  H01L21/049 ,  H01L21/28247 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7816

摘要： A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.

摘要翻译： 介绍了半导体器件。 该器件包括具有碳化硅的半导体层，并具有第一表面和第二表面。 栅极绝缘层设置在半导体层的第一表面的一部分上，栅电极设置在栅极绝缘层上。 该器件还包括设置在栅极绝缘层和栅电极之间的邻近栅电极的边缘的角部处的氧化物，因此栅极绝缘层在角部具有比层的中心处的厚度更大的厚度。 还提供了一种用于制造该装置的方法。