公开(公告)号：US20150132962A1

公开(公告)日：2015-05-14

申请号：US14076386

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Dae-Han CHOI ,  Dae Geun YANG ,  Taejoon HAN ,  Andy WEI

IPC: H01L21/308

CPC classification number: H01L21/0337

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract translation: 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US20150104918A1

公开(公告)日：2015-04-16

申请号：US14050494

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping LIU ,  Jing WAN ,  Andy WEI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract translation: 提出了用于促进半导体器件的制造的方法，例如栅极全能纳米线场效应晶体管。 所述方法包括例如：提供至少一个堆叠结构，其包括在衬底结构上方延伸的至少一个层或凸块; 选择性地氧化所述至少一个堆叠结构的至少一部分以形成至少一个纳米线，所述至少一个纳米线在由所述堆叠结构的氧化材料包围的所述堆叠结构内延伸; 以及从所述堆叠结构中去除所述氧化的材料，暴露所述纳米线。 这种选择性氧化可以包括氧化衬底结构的上部，例如支撑堆叠结构的一个或多个翅片的上部，以促进纳米线的完全360度曝光。 在一个实施例中，堆叠结构包括一个或多个菱形凸块或凸脊。

公开(公告)号：US20150091094A1

公开(公告)日：2015-04-02

申请号：US14043243

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Lun ZHAO ,  Dae Geun YANG ,  Jin Ping LIU ,  Tien-Ying LUO ,  Guillaume BOUCHE ,  Mariappan HARIHARAPUTHIRAN ,  Churamani GAIRE

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。