FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE
    2.
    发明申请
    FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE 审中-公开
    形成来源/排水区域与单一和结果的设备

    公开(公告)号:US20150255353A1

    公开(公告)日:2015-09-10

    申请号:US14197267

    申请日:2014-03-05

    CPC classification number: H01L21/823814 H01L21/823821 H01L27/0924

    Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.

    Abstract translation: 公开了用单个掩模版形成FinFET源极/漏极区域的方法以及所得到的器件。 实施例可以包括在衬底上形成第一鳍片和第二鳍片,形成跨越第一鳍片和第二鳍片的栅极,在栅极的两侧去除第一鳍片和第二鳍片的部分,在第二鳍片上形成硅磷顶部 第一鳍片和第二鳍片代替部分,去除第一鳍片上的磷磷顶部,并且在第一鳍片上形成硅锗顶部代替硅磷顶部。

    STRAINED FIN STRUCTURES AND METHODS OF FABRICATION
    3.
    发明申请
    STRAINED FIN STRUCTURES AND METHODS OF FABRICATION 审中-公开
    应变结构和制造方法

    公开(公告)号:US20150194307A1

    公开(公告)日:2015-07-09

    申请号:US14147666

    申请日:2014-01-06

    Abstract: Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material. The resultant device may have tensile strained fin structures or compressively strained fin structures, or both.

    Abstract translation: 提供了制造应变翅片结构的方法,其包括:在衬底结构上提供虚拟衬底材料,虚拟衬底材料具有虚拟衬底晶格常数和虚拟衬底晶格结构; 在所述虚拟衬底材料的区域上提供第一材料,所述第一材料部分地通过符合所述虚拟衬底晶格结构获得应变的第一材料晶格结构; 并将第一鳍图案蚀刻到第一材料中。 该方法可以包括在虚拟衬底材料的第二区域上提供第二材料,第二材料部分地通过符合虚拟衬底晶格结构并且将鳍状图案蚀刻到第二材料中来获得应变晶格结构。 所得到的装置可以具有拉伸应变翅片结构或压缩应变翅片结构,或两者。

    DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION
    5.
    发明申请
    DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION 有权
    具有自对准FIN形成的FINFET形成装置和方法

    公开(公告)号:US20150091094A1

    公开(公告)日:2015-04-02

    申请号:US14043243

    申请日:2013-10-01

    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

    Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如:获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如:具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

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