公开(公告)号：US20200152531A1

公开(公告)日：2020-05-14

申请号：US16425387

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  G01R31/26

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

公开(公告)号：US20200152530A1

公开(公告)日：2020-05-14

申请号：US16185696

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L21/66 ,  H01L23/528 ,  H01L21/768

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.

公开(公告)号：US10566411B2

公开(公告)日：2020-02-18

申请号：US15834443

申请日：2017-12-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Lin Hu ,  Brian Greene

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768

Abstract: Device structures and fabrication methods for an on-chip resistor. A resistor body is formed on an interlayer dielectric layer of a contact level. A contact is formed that extends vertically through the interlayer dielectric layer. One or more dielectric layers are formed over the contact level, and a metal feature is formed in the one or more dielectric layers. The metal feature is at least in part in direct contact with a portion of the resistor body.

公开(公告)号：US20180269275A1

公开(公告)日：2018-09-20

申请号：US15463465

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Vikrant Chauhan ,  Kong Boon Yeap ,  Ahmed Hassan

IPC: H01L49/02

CPC classification number: H01L28/88

Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

公开(公告)号：US20170213792A1

公开(公告)日：2017-07-27

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.