公开(公告)号：US09583397B1

公开(公告)日：2017-02-28

申请号：US15151720

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Derya Deniz ,  Benjamin G. Moser ,  Sunit S. Mahajan ,  Domingo A. Ferrer Luppi

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/45 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L21/321 ,  H01L21/285 ,  H01L21/266

CPC classification number: H01L21/823814 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/3212 ,  H01L21/3215 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76859 ,  H01L21/76889 ,  H01L21/823871 ,  H01L29/45 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a contact within a dielectric layer to a source/drain terminal of a field-effect-transistor (FET). The contact may include: a titanium-tantalum-silicide at a surface of the source/drain terminal; a barrier layer over the titanium-tantalum-silicide; and a metal over the barrier layer and extending to a top surface of the dielectric layer.

Abstract translation: 本公开的一个方面涉及电介质层中与场效应晶体管（FET）的源极/漏极端子的接触。 接触可以包括：在源极/漏极端子的表面处的钛 - 钽 - 硅化物; 在钛 - 钽 - 硅化物上的阻挡层; 以及阻挡层上的金属并延伸到电介质层的顶表面。

公开(公告)号：US09793216B2

公开(公告)日：2017-10-17

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

公开(公告)号：US20170125509A1

公开(公告)日：2017-05-04

申请号：US14932441

申请日：2015-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer Luppi ,  Aritra Dasgupta ,  Benjamin G. Moser

IPC: H01L49/02

CPC classification number: H01L28/24

Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.

公开(公告)号：US10263065B2

公开(公告)日：2019-04-16

申请号：US14932441

申请日：2015-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Domingo A. Ferrer Luppi ,  Aritra Dasgupta ,  Benjamin G. Moser

IPC: H01L49/02

Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.

公开(公告)号：US20170213792A1

公开(公告)日：2017-07-27

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.