公开(公告)号：US20200027981A1

公开(公告)日：2020-01-23

申请号：US16038265

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Kangguo Cheng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/768

Abstract: A fin cut last methodology for manufacturing a vertical FinFET includes forming a plurality of semiconductor fins over a substrate, forming shallow trench isolation between active fins and, following the formation of a functional gate of the active fins, using a selective etch to remove a sacrificial fin from within an isolation region. A further etching step can be used to remove a portion of the gate stack proximate to the sacrificial fin to create an isolation trench and a laterally-extending cavity within the isolation region that are back-filled with an isolation dielectric.

公开(公告)号：US20180096895A1

公开(公告)日：2018-04-05

申请号：US15284110

申请日：2016-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/66795

Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.

公开(公告)号：US20170053836A1

公开(公告)日：2017-02-23

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

Abstract translation: 一种方法包括提供具有第一和第二多个翅片的基底，其上设置有第一至少一个介电材料，去除第一介电材料的上部以暴露第一和第二多个翅片的上部，去除 第一介电材料从第二多个翅片的下部分暴露以暴露第二多个翅片的下部，在第二多个翅片的至少上部暴露部分和下部暴露部分上沉积第二至少一个电介质材料， 第一多个翅片的上暴露部分，去除第二介电材料以暴露第一和第二多个翅片的上部，并且其中第一介电材料不同于第二介电材料。 所得到的结构可以用作nFET和pFET。

公开(公告)号：US20160315182A1

公开(公告)日：2016-10-27

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Min Gyu SUNG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20150340289A1

公开(公告)日：2015-11-26

申请号：US14687300

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Steven BENTLEY

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/161 ,  H01L21/02 ,  H01L29/165 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/161 ,  H01L29/165

Abstract: Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.

Abstract translation: 提供制造一个或多个半导体鳍片结构的方法，其包括：提供包括第一半导体材料的衬底结构; 在所述衬底结构上方提供散热片堆叠，所述散热片堆叠包括至少一个包括第二半导体材料的半导体层; 在所述散热片堆叠和所述基板结构上沉积保形膜; 以及使用至少部分地将所述散热片堆叠作为掩模来蚀刻所述衬底结构，以便于限定所述一个或多个半导体鳍片结构。 共形保护膜在蚀刻衬底结构期间保护散热片堆叠的至少一个半导体层的侧壁免受蚀刻。 作为一个示例，第一半导体材料可以是或包括硅，第二半导体材料可以是或包括硅锗，并且在一个示例中，保形膜可以是氮化硅。