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    Gate cut method after source/drain metallization
    22.
    发明授权
    Gate cut method after source/drain metallization 有权

    公开(公告)号：US10566201B1

    公开(公告)日：2020-02-18

    申请号：US16174510

    申请日：2018-10-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chanro Park ,  Ruilong Xie ,  Hui Zang ,  Laertis Economikos ,  Andre LaBonte

    IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66

    Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.

    Field effect transistors with self-aligned metal plugs and methods
    24.
    发明授权
    Field effect transistors with self-aligned metal plugs and methods 有权

    公开(公告)号：US10553486B1

    公开(公告)日：2020-02-04

    申请号：US16047037

    申请日：2018-07-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

    IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/321

    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

    FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED METAL PLUGS AND METHODS
    25.
    发明申请
    FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED METAL PLUGS AND METHODS 审中-公开

    公开(公告)号：US20200035555A1

    公开(公告)日：2020-01-30

    申请号：US16047037

    申请日：2018-07-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

    IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45

    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

    Using source/drain contact cap during gate cut
    27.
    发明授权
    Using source/drain contact cap during gate cut 有权

    公开(公告)号：US10522538B1

    公开(公告)日：2019-12-31

    申请号：US16032108

    申请日：2018-07-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

    IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

    Performing concurrent diffusion break, gate and source/drain contact cut etch processes
    28.
    发明授权
    Performing concurrent diffusion break, gate and source/drain contact cut etch processes 有权

    公开(公告)号：US10522410B2

    公开(公告)日：2019-12-31

    申请号：US15958593

    申请日：2018-04-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang ,  Hong Yu

    IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088

    Abstract: A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.

    METHODS OF FORMING GATE CONTACT OVER ACTIVE REGION FOR VERTICAL FINFET, AND STRUCTURES FORMED THEREBY
    29.
    发明申请
    METHODS OF FORMING GATE CONTACT OVER ACTIVE REGION FOR VERTICAL FINFET, AND STRUCTURES FORMED THEREBY 审中-公开

    公开(公告)号：US20190393342A1

    公开(公告)日：2019-12-26

    申请号：US16018970

    申请日：2018-06-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Hui Zang ,  Steven R. Soss

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L27/06

    Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.

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