FIN-BASED LATERAL BIPOLAR JUNCTION TRANSISTOR AND METHOD

    公开(公告)号:US20230066963A1

    公开(公告)日:2023-03-02

    申请号:US17537564

    申请日:2021-11-30

    Abstract: In a disclosed semiconductor structure, a lateral bipolar junction transistor (BJT) has a base positioned laterally between a collector and an emitter. The base includes a semiconductor fin with a first portion that extends from a substrate through an isolation layer, a second portion on the first portion, and a third portion on the second portion. The collector and emitter are on the isolation layer and positioned laterally immediately adjacent to opposing sidewalls of the second portion of the semiconductor fin. In some embodiments, the BJT is a standard BJT where the semiconductor fin (i.e., the base), the collector, and the emitter are made of the same semiconductor material. In other embodiments, the BJT is a heterojunction bipolar transistor (HBT) where a section of the semiconductor fin (i.e., the base) is made of a different semiconductor material for improved performance. Also disclosed is a method of forming the structure.

    Bipolar transistor structure on semiconductor fin and methods to form same

    公开(公告)号:US12176426B2

    公开(公告)日:2024-12-24

    申请号:US17657154

    申请日:2022-03-30

    Abstract: Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

    Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials

    公开(公告)号:US11810951B2

    公开(公告)日:2023-11-07

    申请号:US17552386

    申请日:2021-12-16

    Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

    SEMICONDUCTOR-ON-INSULATOR FIELD EFFECT TRANSISTOR WITH PERFORMANCE-ENHANCING SOURCE/DRAIN SHAPES AND/OR MATERIALS

    公开(公告)号:US20230197783A1

    公开(公告)日:2023-06-22

    申请号:US17552386

    申请日:2021-12-16

    CPC classification number: H01L29/0847 H01L29/7848 H01L29/66568 H01L29/0653

    Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

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