公开(公告)号：US5586274A

公开(公告)日：1996-12-17

申请号：US217687

申请日：1994-03-24

申请人： William R. Bryg ,  Craig R. Frink ,  Larry N. McMahan ,  Helen Nusbaum

发明人： William R. Bryg ,  Craig R. Frink ,  Larry N. McMahan ,  Helen Nusbaum

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F13/36 ,  G06F13/00

CPC分类号： G06F13/36

摘要： A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on the bus, and a bus controller that limits the types of transactions that can be sent on the bus at any given time. When one module is performing an atomic operation, the bus controller limits transactions to those that do not change the memory image that existed when the atomic operation was commenced. The bus controller, however, permits responses or returns of data, assuming the response or return does not alter the current value of data.

摘要翻译： 一种拆分事务总线系统，可以在不锁定总线的情况下适应原子操作，并且在原子操作期间不存在死锁的可能性。 总线系统可以用于包括总线，在总线上彼此发送事务的组件模块的总线控制器的总线控制器，该总线控制器限制在任何给定时间可以在总线上发送的事务的类型。 当一个模块执行原子操作时，总线控制器将事务限制为不改变原子操作开始时存在的存储器映像的事务。 但是，总线控制器允许响应或返回数据，假设响应或返回不会改变当前的数据值。

公开(公告)号：US5530933A

公开(公告)日：1996-06-25

申请号：US201463

申请日：1994-02-24

申请人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

发明人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0831

摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

摘要翻译： 与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。 每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。 每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。 每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。 当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

公开(公告)号：US5528766A

公开(公告)日：1996-06-18

申请号：US217500

申请日：1994-03-24

申请人： Michael L. Ziegler ,  John F. Shelton ,  William R. Bryg

发明人： Michael L. Ziegler ,  John F. Shelton ,  William R. Bryg

IPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/14

CPC分类号： G06F13/36

摘要： A multiple round-robin arbitration scheme for a shared bus system that ensures forward progress by each component utilizing the shared bus. In the shared bus system, component modules arbitrate for control of the bus for one or more cycles, and send transactions on the bus during cycles in which they control the bus. The transactions are divided into a set of transaction classes. Certain classes of transactions cannot be issued during certain bus cycles. In certain other cycles, transactions of any class may be issued. The multiple round-robin arbitration scheme ensures forward progress by ensuring that each module seeking to issue a transaction of a given class obtains control of the bus during a cycle when transactions of that class can be issued.

摘要翻译： 一种共享总线系统的多循环仲裁方案，确保每个组件利用共享总线的前进进程。 在共享总线系统中，组件模块仲裁一个或多个周期的总线控制，并在总线控制总线的周期期间在总线上发送事务。 交易分为一组交易类。 在某些公交车周期内不能发出某些类别的交易。 在某些其他周期中，任何类别的交易都可能被发行。 多轮循环仲裁方案通过确保寻求发出给定类别的交易的每个模块在可以发出该类交易的一个周期内获得对总线的控制，从而确保前进进展。

公开(公告)号：US4739471A

公开(公告)日：1988-04-19

申请号：US750701

申请日：1985-06-28

申请人： Allen J. Baum ,  William R. Bryg

发明人： Allen J. Baum ,  William R. Bryg

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/35 ,  G06F9/45 ,  G06F12/02 ,  G06F12/08 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F8/41 ,  G06F9/35

摘要： A basic instruction for moving a string of bytes in a word has been devised. Because the operations in the instruction are basic, very few variations are necessary to accommodate diversity of lengths and variables. These operations are imbedded in a single code sequence; the compiler can therefore generate exactly the minimum sequence necessary to perform the operations and can precompute many of the operands at compile time, typically completing the instruction within a single cycle time. The control necessary to optimize the operations is then in the compiler instead of the hardware.

摘要翻译： 已经设计了用于移动单词中字节串的基本指令。 由于指令中的操作是基本操作，因此需要极少的变化来适应长度和变量的多样性。 这些操作嵌入在一个代码序列中; 因此，编译器可以精确地生成执行操作所需的最小序列，并且可以在编译时预先计算许多操作数，通常在单个周期内完成指令。 然后在编译器而不是硬件中进行优化操作所需的控制。

公开(公告)号：US6108721A

公开(公告)日：2000-08-22

申请号：US107008

申请日：1998-06-29

申请人： William R. Bryg ,  Monish S. Shah ,  Thomas V. Spencer

发明人： William R. Bryg ,  Monish S. Shah ,  Thomas V. Spencer

IPC分类号： G06F12/08 ,  G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F13/122 ,  G06F12/0835 ,  G06F13/28

摘要： In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.

摘要翻译： 在确保I / O通道与处理器之间的数据一致性的方法和装置中，当接收到DMA完成通知时，系统软件发出导致事务发生的指令。 事务指示I / O通道强制执行一致性，然后仅在确保一致性后才响应。 具体来说，DMA-SYNC事务被广播到系统中的所有I / O通道。 响应于此，每个I / O通道将其缓存中的任何修改的行写回存储器，该行可能包含系统报告的完成的DMA序列的DMA数据。 I / O通道具有报告方式来指示此事务何时完成，以便DMA-SYNC事务不必以流水线顺序完成。 因此，在响应DMA-SYNC事务之前，I / O通道可以发出新的事务。

公开(公告)号：US5724538A

公开(公告)日：1998-03-03

申请号：US607622

申请日：1996-02-27

申请人： Dale C. Morris ,  Jerome C. Huck ,  William R. Bryg

发明人： Dale C. Morris ,  Jerome C. Huck ,  William R. Bryg

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1018

摘要： The present invention relates to the design of computer systems incorporating virtual memory where a virtual page number is longer than the inherent basic data width of the designed computer system. Instead of storing an entire tag in page table entries, a reduced tag is stored. The reduced tag is sized to be no greater in length than the basic computer data width and therefore a single compare operation will ascertain whether there is a match between the reduced tag and the tag stored in a page table entry. To maintain uniqueness of the page table entries, any bits removed from the virtual address to form the reduced tag are used to form an index into the page table.

摘要翻译： 本发明涉及包含虚拟存储器的计算机系统的设计，其中虚拟页码长于设计的计算机系统的固有基本数据宽度。 代替在页表条目中存储整个标签，而不是存储缩小的标签。 缩小标签的大小的长度不应大于基本计算机数据宽度，因此单个比较操作将确定缩小的标签与存储在页表条目中的标签之间是否存在匹配。 为了保持页表项的唯一性，使用从虚拟地址中删除以形成缩减标记的任何位来形成页表中的索引。

公开(公告)号：US5603004A

公开(公告)日：1997-02-11

申请号：US196042

申请日：1994-02-14

申请人： Gordon Kurpanek ,  Eric Delano ,  Michael A. Buckley ,  William R. Bryg

发明人： Gordon Kurpanek ,  Eric Delano ,  Michael A. Buckley ,  William R. Bryg

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/0862

摘要： A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.

摘要翻译： 缓存系统缓冲存储在主存储器中并由处理器使用的数据。 高速缓存系统包括第一高速缓存，第二高速缓存，第一传送通道，第二传送通道和第三传送通道。 第一个缓存是完全关联的。 第二个缓存直接映射。 第一个传输通道将数据线从主存储器传输到第一个缓存。 第二传输信道将数据线从第一高速缓存传送到第二高速缓存。 第三传送通道将数据线从第二高速缓存传送到主存储器。 并行执行来自第一高速缓存和第二高速缓存的数据线的访问。

公开(公告)号：US4914582A

公开(公告)日：1990-04-03

申请号：US879707

申请日：1986-06-27

申请人： William R. Bryg ,  Russell Kao

发明人： William R. Bryg ,  Russell Kao

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0864 ,  G06F12/127

摘要： A method of retrieving data from a multi-set cache memory in a computer system. An address, which includes an index, is presented by the processor to the cache memory. The index is utilized to access the cache to generate an output which includes a block corresponding to the index from each set of the cache. Each block includes an address tag and data. A portion of the address tag for all but one of the blocks is compared with a corresponding portion of the address. If the comparison results in a match, then the data from the block associated with match is provided to the processor. If the comparison does not result in a match, then the data from the remaining block is provided to the processor. A full address tag comparison is done in parallel with the "lookaside tag" comparison to confirm a "hit."

摘要翻译： 一种从计算机系统中的多组高速缓冲存储器检索数据的方法。 包括索引的地址由处理器呈现给高速缓冲存储器。 索引用于访问高速缓存以生成包括与每个高速缓存组的索引相对应的块的输出。 每个块包括地址标签和数据。 除了一个块之外的所有地址标签的一部分与地址的相应部分进行比较。 如果比较导致匹配，则将与匹配相关联的块的数据提供给处理器。 如果比较不导致匹配，则将剩余块的数据提供给处理器。 完整的地址标签比较与“后备标签”比较并行进行，以确认“命中”。

公开(公告)号：US4777589A

公开(公告)日：1988-10-11

申请号：US750578

申请日：1985-06-28

申请人： Steven C. Boettner ,  William R. Bryg ,  David V. James ,  Tso-Kai Liu ,  Michael J. Mahon ,  Terrence C. Miller ,  William S. Worley, Jr.

发明人： Steven C. Boettner ,  William R. Bryg ,  David V. James ,  Tso-Kai Liu ,  Michael J. Mahon ,  Terrence C. Miller ,  William S. Worley, Jr.

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F12/14 ,  G06F12/08

CPC分类号： G06F12/1475 ,  G06F12/0292 ,  G06F12/0653 ,  G06F2212/206

摘要： A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

公开(公告)号：US06049851A

公开(公告)日：2000-04-11

申请号：US196618

申请日：1994-02-14

申请人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

发明人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

IPC分类号： G06F12/08 ,  G06F9/34

CPC分类号： G06F12/0831

摘要： A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

摘要翻译： 具有高速缓存和相干I / O和多处理器计算机系统的单处理器计算机系统中的双缓存窥探机制减少了在一致性检查期间处理器停顿的周期数。 侦听机制分割每个相关性检查，以便首先将只读检查发送到高速缓存子系统，然后只有在只读检查期间存在高速缓存命中时才会发送读写检查，并且存在 需要修改缓存。 即使缓存命中导致额外的一致性检查，平均处理器流水线停止时间也减少，因为大多数一致性检查不会导致缓存命中。