公开(公告)号：US06810347B2

公开(公告)日：2004-10-26

申请号：US10340014

申请日：2003-01-09

申请人： Peter Chambers

发明人： Peter Chambers

IPC分类号： G01R3100

CPC分类号： G06F11/1441 ,  G07C1/02

摘要： A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a partitioned memory configuration is implemented to backup the data word and its associated error correction code to the non-volatile memory. In this way the non-volatile memory is able to store a range of counts whose maximum number far exceeds the memory's endurance limit.

公开(公告)号：US06230216B1

公开(公告)日：2001-05-08

申请号：US09239461

申请日：1999-01-28

申请人： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

发明人： Peter Chambers ,  Subramanian S. Meiyappan ,  Swaroop Adusumilli

IPC分类号： G06F300

CPC分类号： G06F9/30043 ,  G06F9/3875 ,  G06F12/06 ,  G06F13/423

摘要： A system and method for using single address cycles and eliminating dual address cycles to transmit a target address in a computer system. The computer system comprises a bus, a central processing unit coupled to the bus, an initiator device coupled to the bus, and a target device coupled to the bus. The target device comprises a first configuration register which is adapted to use a configuration bit to indicate an address range of the target device. The central processing unit interrogates the first configuration register and communicates the address range indicated by the configuration bit to the initiator device. The initiator device comprises a second configuration register which is adapted to use a configuration bit to register the address range of the target device. The initiator device is adapted to disable its dual address cycle capability and transmit to the target device the target address in a single address cycle provided that the address range of the target device as indicated by the respective configuration bits in the first and second configuration registers is not less than a size of the target address.

摘要翻译： 一种用于使用单个地址周期并消除双地址周期以在计算机系统中传送目标地址的系统和方法。 计算机系统包括总线，耦合到总线的中央处理单元，耦合到总线的启动器设备以及耦合到总线的目标设备。 目标设备包括第一配置寄存器，其适于使用配置位来指示目标设备的地址范围。 中央处理单元询问第一配置寄存器，并将配置位指示的地址范围传送给启动器设备。 启动器设备包括第二配置寄存器，其适于使用配置位来注册目标设备的地址范围。 启动器设备适于禁用其双地址周期能力并且以单个地址周期向目标设备发送目标地址，只要如第一和第二配置寄存器中的相应配置位所指示的目标设备的地址范围是 不小于目标地址的大小。

公开(公告)号：US5949251A

公开(公告)日：1999-09-07

申请号：US904918

申请日：1997-08-01

申请人： Peter Chambers

发明人： Peter Chambers

IPC分类号： G05B19/045 ,  H03K19/173

CPC分类号： G05B19/045 ,  G05B2219/23289

摘要： The present invention allows the behavior of a state machine to be readily modified by software after it has been fabricated in silicon. To perform these modifications, the present invention uses special patch registers, multiplexers, and comparators to bypass certain states within the sequence of states within the combinatorial logic of the state machine and/or add new state sequences. Each patch register stores a state to be patched, a next state, and outputs. The state to be patched is the state that will be modified, while the next state is the state the state machine transitions into from the state to be patched, and the outputs are the outputs generated and asserted by the state machine while within the next state. Many such patch registers can be used by the present invention to define many modifications. Using this patch mechanism, the present invention allows new states to be added and existing states to be removed from the sequence of states that the state machine cycles through. To implement the functionality of the patch registers within the present invention, a separate comparator is connected to each patch register to determine when the present state of the state machine matches the state to be patched as stored within each respective patch register. When these values match, the corresponding comparator sends control signals causing the multiplexers to transfer into the state machine the next state and outputs as stored within that particular patch register that matched.

摘要翻译： 本发明允许状态机的行为在其被制造成硅之后被软件容易地修改。 为了执行这些修改，本发明使用特殊的片段寄存器，复用器和比较器绕过状态机的组合逻辑内的状态序列内的某些状态和/或添加新的状态序列。 每个补丁寄存器存储待修补的状态，下一个状态和输出。 要修补的状态是将被修改的状态，而下一状态是状态机从要修补的状态转变的状态，并且输出是在下一状态期间由状态机产生和断言的输出 。 本发明可以使用许多这种补丁寄存器来定义许多修改。 使用该补丁机制，本发明允许添加新的状态，并且从状态机循环的状态序列中去除现有状态。 为了实现本发明中的补丁寄存器的功能，单独的比较器连接到每个补丁寄存器，以确定状态机的当前状态何时与每个相应补丁寄存器中存储的待修补状态相匹配。 当这些值匹配时，相应的比较器发送控制信号，导致多路复用器将其转移到状态机下一个状态，并输出存储在匹配的特定补丁寄存器中。

公开(公告)号：US5870570A

公开(公告)日：1999-02-09

申请号：US740501

申请日：1996-10-29

申请人： Peter Chambers ,  Edward Michael Petryk ,  George Parker Crouse

发明人： Peter Chambers ,  Edward Michael Petryk ,  George Parker Crouse

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/00 ,  G06F13/20

CPC分类号： G06F13/364

摘要： A multiple peripheral component interconnect (PCI) agent integrated circuit device for connecting to an external PCI bus. In one embodiment, the present multiple PCI agent integrated circuit device includes, an integrated circuit which is adapted to be coupled to an external PCI bus. The integrated circuit includes an internal PCI bus built in. The internal PCI bus is adapted to transmit data signals thereon, and is further adapted to couple to the external PCI bus via a connector. A plurality of PCI agents are built into the integrated circuit, wherein each of the plurality of PCI agents are capable of performing an independent function. Each of the plurality of PCI agents are coupled to the internal PCI bus. A predictive arbiter is built into the integrated circuit and is coupled to both the internal PCI bus and to the plurality of PCI agents. The predictive arbiter arbitrates between the PCI agents for ownership of the internal PCI bus.

摘要翻译： 用于连接到外部PCI总线的多外围部件互连（PCI）代理集成电路装置。 在一个实施例中，本多个PCI代理集成电路器件包括适于耦合到外部PCI总线的集成电路。 集成电路包括内置的PCI总线。内部PCI总线适于在其上传输数据信号，并且还适于经由连接器耦合到外部PCI总线。 多个PCI代理内置在集成电路中，其中多个PCI代理中的每一个能够执行独立的功能。 多个PCI代理中的每一个耦合到内部PCI总线。 预测仲裁器内置在集成电路中，并且耦合到内部PCI总线和多个PCI代理。 预测仲裁者在内部PCI总线的所有权的PCI代理之间进行仲裁。

公开(公告)号：US5845130A

公开(公告)日：1998-12-01

申请号：US712089

申请日：1996-09-11

申请人： Lonnie C. Goff ,  Peter Chambers

发明人： Lonnie C. Goff ,  Peter Chambers

IPC分类号： G06F13/16 ,  G06F15/167 ,  G06F12/02

CPC分类号： G06F13/1663 ,  G06F15/167

摘要： A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory. Once the first processor controls access to the shared memory, the second processor knows that it must wait before attempting to control access to the shared memory. In so doing, the present invention eliminates contention between the first and second processors for control of the shared memory.

摘要翻译： 一种用于防止共享存储器环境中的竞争的系统和方法。 在一个实施例中，第一处理器读取耦合到共享存储器和第二处理器的业务控制器。 第一处理器将其标识符写入流量控制器，只要流量控制器不具有与其中存储的第二处理器相对应的标识符。 如果交通控制器具有与其中存储的第二处理器相对应的标识符，则第一处理器周期性地读取业务控制器，直到业务控制器没有与其中存储的第二处理器相对应的标识符。 一旦流量控制器具有与其中存储的第一处理器相对应的标识符，则流量控制器允许第一处理器控制对共享存储器的访问。 一旦第一处理器控制对共享存储器的访问，则第二处理器知道在尝试控制对共享存储器的访问之前它必须等待。 这样做，本发明消除了用于共享存储器的控制的第一和第二处理器之间的争用。

公开(公告)号：US07370069B2

公开(公告)日：2008-05-06

申请号：US10759786

申请日：2004-01-15

申请人： Peter Chambers ,  Joseph James Judkins, III

发明人： Peter Chambers ,  Joseph James Judkins, III

IPC分类号： G06F15/00

CPC分类号： G06F1/0356

摘要： A device for performing numerical value conversion of a digital input value in a first unit to a second unit being a natural unit includes a look-up table storing an array of coefficients for performing the numerical value conversion. The look-up table is indexed using a first parameter to provide a selected coefficient. An arithmetic logic unit (ALU) is coupled to receive the digital input value and the selected coefficient and perform the numerical value conversion based on a first equation using the selected coefficient to compute a digital output value in the second unit. The first unit can be an arbitrary ADC unit and the second unit is a natural unit of physical measurement, such as volts, amperes, degree Centigrade. Furthermore, the device can be used to perform numerical value conversion from the arbitrary unit to the natural unit having a linear or a non-linear relationship.

摘要翻译： 用于将第一单元中的数字输入值数值转换为作为自然单元的第二单元的设备包括存储执行数值转换的系数阵列的查找表。 使用第一参数来索引查找表以提供所选择的系数。 耦合算术逻辑单元（ALU）以接收数字输入值和所选择的系数，并且使用所选择的系数基于第一等式执行数值转换，以计算第二单元中的数字输出值。 第一个单元可以是任意的ADC单元，第二个单元是物理测量的自然单位，如伏特，安培，摄氏度。 此外，该装置可以用于执行从任意单元到具有线性或非线性关系的自然单元的数值转换。

公开(公告)号：US07245148B2

公开(公告)日：2007-07-17

申请号：US11237287

申请日：2005-09-27

申请人： Thruston Awalt ,  Peter Chambers

发明人： Thruston Awalt ,  Peter Chambers

IPC分类号： G06F7/38

CPC分类号： H03K19/1732

摘要： A circuit in an integrated circuit having an input terminal to be coupled to a resistor network for selecting one of multiple digital states in the integrated circuit includes a voltage decode circuit, a control circuit and a power-up control circuit. The first input terminal receives an input voltage having a voltage value associated with the multiple digital states. The voltage decode circuit receives the input voltage and generates a voltage decode signal indicative of the voltage value of the input voltage. The control circuit receives the voltage decode signal and generates an output control signal accordingly where the output control signal selects one of the multiple digital states. The power-up control circuit provides power to the resistor network, the voltage decode circuit and the control circuit for determining the selected digital state and disconnects power to those circuits after the selected digital state is determined.

摘要翻译： 具有要耦合到电阻网络的输入端子用于选择集成电路中的多个数字状态之一的集成电路中的电路包括电压解码电路，控制电路和上电控制电路。 第一输入端子接收具有与多个数字状态相关联的电压值的输入电压。 电压解码电路接收输入电压并产生指示输入电压的电压值的电压解码信号。 控制电路接收电压解码信号并相应地产生输出控制信号，其中输出控制信号选择多个数字状态之一。 上电控制电路为电阻网络，电压解码电路和控制电路提供电力，用于确定所选择的数字状态，并在确定所选择的数字状态之后断开对那些电路的电力。

公开(公告)号：US07203213B2

公开(公告)日：2007-04-10

申请号：US10759987

申请日：2004-01-15

申请人： Douglas P. Anderson ,  Peter Chambers ,  Joseph J. Judkins, III ,  William Andrew Burkland

发明人： Douglas P. Anderson ,  Peter Chambers ,  Joseph J. Judkins, III ,  William Andrew Burkland

IPC分类号： H01S3/00

CPC分类号： H01S5/0683 ,  H01S5/0428 ,  H01S5/06825

摘要： An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control.

摘要翻译： 加速器电路被并入激光二极管系统中，用于加速激光二极管的导通操作，而与激光二极管系统的控制回路带宽无关。 加速器电路在激光接通时向补偿电容器提供升压电流，补偿电容器用于建立激光二极管系统的控制回路带宽。 升压电流使控制环能够快速增加激光二极管的偏置电流。 当激光二极管达到所需的工作点时，升压电流终止，激光二极管系统的控制回路恢复正常的偏置电流控制。 在一个实施例中，加速器电路包括控制电流源以实现开环开启控制的定时器电路。 在另一个实施例中，加速器电路包括与单触发逻辑电路结合工作以提供闭环控制的比较器电路。

公开(公告)号：US07126513B1

公开(公告)日：2006-10-24

申请号：US11237166

申请日：2005-09-27

申请人： Ray Zinn ,  Peter Chambers ,  Scott Brown

发明人： Ray Zinn ,  Peter Chambers ,  Scott Brown

IPC分类号： H03M1/84

CPC分类号： G06F1/22 ,  H04L25/062

摘要： A circuit and method for programming and control of an integrated circuit includes a control pin receiving an applied input voltage selected from a set of predetermined programming voltages and an on-chip control voltage decode circuit to select one of multiple programming states for the integrated circuit based on the applied input voltage. In one embodiment, an off-chip voltage divider is used to establish the set of predetermined programming voltages. The on-chip control voltage decode circuit includes a voltage divider to generate comparison voltage levels for detecting the voltage level of the input voltage for selecting the desired programming state. The comparison voltage levels include voltages having voltage values that are midway between pairs of adjacent programming voltages. The voltage decode circuit includes a control circuit receiving comparison results from comparators and generating an output control signal for selecting the desired digital state based on the comparison results.

摘要翻译： 用于集成电路的编程和控制的电路和方法包括控制引脚，其接收从一组预定编程电压中选择的施加的输入电压和片上控制电压解码电路，以选择用于集成电路的多个编程状态之一 对应用的输入电压。 在一个实施例中，使用片外分压器来建立一组预定的编程电压。 片上控制电压解码电路包括分压器，以产生用于检测用于选择所需编程状态的输入电压的电压电平的比较电压电平。 比较电压电平包括具有在相邻编程电压对之间的中间电压值的电压。 电压解码电路包括控制电路，其接收比较器的比较结果，并根据比较结果生成用于选择所需数字状态的输出控制信号。

公开(公告)号：US07102394B1

公开(公告)日：2006-09-05

申请号：US11237214

申请日：2005-09-27

申请人： Paul Wilson ,  Peter Chambers

发明人： Paul Wilson ,  Peter Chambers

IPC分类号： G01R19/00 ,  G05F1/44

CPC分类号： G06F1/22

摘要： A circuit in an integrated circuit having input terminals coupled to a resistor network for selecting one of multiple digital states includes a tri-state circuit, a multiplexer, a comparator and a control circuit. A DAC can be used to generate a set of comparison voltage levels. The circuit detects the power connection and the resistance values of at least two resistors in the resistor network having a third resistor of fixed resistance. The resistance values for the two resistors are selected from a set of resistance values corresponding to the number of digital stages which can be programmed on each terminal. The power connection option doubles the number of digital stages to be programmed on each terminal. Thus, multiple programming states can be assigned to each control pin of an integrated circuit and a large number of programming states can be programmed using a small number of control pins.

摘要翻译： 具有耦合到电阻器网络的输入端子用于选择多个数字状态之一的集成电路中的电路包括三态电路，多路复用器，比较器和控制电路。 可以使用DAC来产生一组比较电压电平。 该电路检测电阻器网络中的至少两个电阻器的电源连接和电阻值，该电阻器具有固定电阻的第三电阻器。 两个电阻器的电阻值从对应于每个端子上可编程的数字级数的一组电阻值中选择。 电源连接选项使每个终端上要编程的数字级数增加一倍。 因此，可以将多个编程状态分配给集成电路的每个控制引脚，并且可以使用少量的控制引脚来编程大量编程状态。