公开(公告)号：US07126513B1

公开(公告)日：2006-10-24

申请号：US11237166

申请日：2005-09-27

申请人： Ray Zinn ,  Peter Chambers ,  Scott Brown

发明人： Ray Zinn ,  Peter Chambers ,  Scott Brown

IPC分类号： H03M1/84

CPC分类号： G06F1/22 ,  H04L25/062

摘要： A circuit and method for programming and control of an integrated circuit includes a control pin receiving an applied input voltage selected from a set of predetermined programming voltages and an on-chip control voltage decode circuit to select one of multiple programming states for the integrated circuit based on the applied input voltage. In one embodiment, an off-chip voltage divider is used to establish the set of predetermined programming voltages. The on-chip control voltage decode circuit includes a voltage divider to generate comparison voltage levels for detecting the voltage level of the input voltage for selecting the desired programming state. The comparison voltage levels include voltages having voltage values that are midway between pairs of adjacent programming voltages. The voltage decode circuit includes a control circuit receiving comparison results from comparators and generating an output control signal for selecting the desired digital state based on the comparison results.

摘要翻译： 用于集成电路的编程和控制的电路和方法包括控制引脚，其接收从一组预定编程电压中选择的施加的输入电压和片上控制电压解码电路，以选择用于集成电路的多个编程状态之一 对应用的输入电压。 在一个实施例中，使用片外分压器来建立一组预定的编程电压。 片上控制电压解码电路包括分压器，以产生用于检测用于选择所需编程状态的输入电压的电压电平的比较电压电平。 比较电压电平包括具有在相邻编程电压对之间的中间电压值的电压。 电压解码电路包括控制电路，其接收比较器的比较结果，并根据比较结果生成用于选择所需数字状态的输出控制信号。

公开(公告)号：US20070139076A1

公开(公告)日：2007-06-21

申请号：US11676070

申请日：2007-02-16

申请人： Peter Chambers

发明人： Peter Chambers

IPC分类号： H03K19/00

CPC分类号： H03K19/1731 ,  H01L2224/49113

摘要： A circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package pin, the pad management circuit couples the first data signal as the second data signal and couples the first output enable signal as the second output enable signal. When the configuration signal indicates the I/O pad is to be left unconnected, the pad management circuit asserts the second output enable signal and generates the second data signal having a predetermined value.

摘要翻译： 一种耦合到包括输入缓冲器，输出缓冲器和焊盘管理电路的集成电路中的输入 - 输出接合焊盘（I / O焊盘）的电路。 焊盘管理电路接收第一数据信号，第一输出使能信号和表示I / O焊盘的连接状态的配置信号，并产生第二数据信号和第二输出使能信号。 当配置信号指示将I / O焊盘连接到封装引脚时，焊盘管理电路将第一数据信号作为第二数据信号耦合，并将第一输出使能信号耦合作为第二输出使能信号。 当配置信号指示I / O焊盘不连接时，焊盘管理电路确定第二输出使能信号并产生具有预定值的第二数据信号。

公开(公告)号：US20050131973A1

公开(公告)日：2005-06-16

申请号：US10759988

申请日：2004-01-15

申请人： Peter Chambers ,  Joseph Judkins

发明人： Peter Chambers ,  Joseph Judkins

IPC分类号： G06F7/00

CPC分类号： H03M1/1235 ,  H03M1/129

摘要： A device for performing numerical value conversion of a digital input value in a first unit to a second, natural unit where the digital input value is a digitized value of a first measurement parameter includes a look-up table storing an array of coefficients for performing the numerical value conversion for multiple measurement parameters. The look-up table is indexed using a first parameter indicative of the first measurement parameter to provide a selected coefficient. The device further includes an arithmetic logic unit (ALU) receiving the digital input value and the selected coefficient and performing the numerical value conversion based on a first equation and the selected coefficient to compute a digital output value. The device also includes a saturation-limit circuit coupled to receive the digital output value from the arithmetic logic unit and provide a predetermined output value when the digital output value exceeds a predetermined maximum value.

摘要翻译： 一种用于对第一单元中的数字输入值进行数值转换的装置，其中数字输入值是第一测量参数的数字化值的第二自然单元包括：存储用于执行第一测量参数的系数阵列的查找表; 多个测量参数的数值转换。 使用指示第一测量参数的第一参数来索引查找表以提供所选择的系数。 该装置还包括接收数字输入值和所选系数的算术逻辑单元（ALU），并且基于第一方程和所选择的系数执行数值转换以计算数字输出值。 该装置还包括饱和极限电路，其被耦合以从所述算术逻辑单元接收所述数字输出值，并且当所述数字输出值超过预定最大值时提供预定的输出值。

公开(公告)号：US06898680B2

公开(公告)日：2005-05-24

申请号：US10336296

申请日：2003-01-03

申请人： Peter Chambers

发明人： Peter Chambers

IPC分类号： G06F12/00 ,  G06F12/12 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/349

摘要： A method and structure are provided that reduce the overall time of the read-erase-modify-write cycle time of non-volatile memories. Specifically, the erase operation of the read-erase-write cycle is avoided in certain circumstances. In one embodiment, the erase operation is skipped where a predetermined pattern is found in at least a portion the block. In another embodiment, the erase operation is skipped where a status of the block indicates that the erase operation can be skipped.

摘要翻译： 提供了减少非易失性存储器的读擦除修改 - 写周期时间的总时间的方法和结构。 具体地说，在某些情况下避免了擦写写周期的擦除操作。 在一个实施例中，擦除操作被跳过，其中在块的至少一部分中发现预定模式。 在另一个实施例中，跳过擦除操作，其中块的状态指示可以跳过擦除操作。

公开(公告)号：US06289406B1

公开(公告)日：2001-09-11

申请号：US09187325

申请日：1998-11-06

申请人： Peter Chambers ,  Swaroop Adusumilli ,  Subramanian S. Meiyappan

发明人： Peter Chambers ,  Swaroop Adusumilli ,  Subramanian S. Meiyappan

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period. The target device is adapted to maintain the access to the initiator device during the dynamic target latency period. Thus, in accordance with the present invention, the target latency is dynamically measured and used to optimize the retry behavior of the initiator and target devices.

摘要翻译： 一种用于完成计算机系统中的发起者设备和主机存储设备之间的读取事务的系统和方法，其中本发明优化了发起者设备和目标设备的重试行为。 本发明的系统包括总线桥装置，其中总线桥装置包括经由总线耦合到启动器装置的目标装置; 主机存储设备耦合到总线桥接器件; 以及耦合到目标设备的定时器机构。 启动器设备适于经由目标设备发起当前读取事务，使得在发起者设备和目标设备之间确认访问。 定时器机构适于测量当前读取事务之前的一个或多个读取事务的目标延迟，并且定时器机制还适于使用目标等待时间来计算动态目标等待时间周期。 目标设备适于在动态目标潜伏期期间维持对发起者设备的访问。 因此，根据本发明，动态测量目标延迟并用于优化发起者和目标设备的重试行为。

公开(公告)号：US6016315A

公开(公告)日：2000-01-18

申请号：US846294

申请日：1997-04-30

申请人： Peter Chambers ,  Scott E. Harrow

发明人： Peter Chambers ,  Scott E. Harrow

IPC分类号： H04L12/56 ,  H04L12/50

CPC分类号： H04L49/90

摘要： A virtual contiguous system for combining multiple and arbitrarily-sized and aligned digital data packets from a PCI bus to a DSP circuit is disclosed. Information from the PCI bus is supplied directly to a plurality of FIFO RAM memory units. Each packet of digital data includes data packet descriptors identifying at least the start address for each data packet and the size of each data packet. The system utilizes this information to operate a read pointer and a write pointer to remove data from the FIFO RAM memory units on a sequential bit-by-bit basis and to supply said data packets to said RAM memory units by means of a write pointer operated by said control circuit. The information transfer is managed on the read side of the FIFO RAM memory units with minimal processing on the write side.

摘要翻译： 公开了一种虚拟连续系统，用于将来自PCI总线的多个和任意大小和对准的数字数据分组组合到DSP电路。 来自PCI总线的信息被直接提供给多个FIFO RAM存储器单元。 每个数字数据包包括至少标识每个数据包的起始地址和每个数据包的大小的数据包描述符。 系统利用该信息来操作读指针和写指针，以逐位逐位地从FIFO RAM存储器单元中移除数据，并通过写指针来将所述数据分组提供给所述RAM存储器单元 由所述控制电路。 信息传输在FIFO RAM存储器单元的读取端以最小的写入侧处理来管理。

公开(公告)号：US5961640A

公开(公告)日：1999-10-05

申请号：US838021

申请日：1997-04-22

申请人： Peter Chambers ,  Scott Edward Harrow ,  David Evoy

发明人： Peter Chambers ,  Scott Edward Harrow ,  David Evoy

IPC分类号： G06F7/76 ,  G06F13/40 ,  G06F17/00

CPC分类号： G06F7/768 ,  G06F13/4013

摘要： An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data. In one embodiment, a byte stream is generated over the output bus. Alternatively, dwords are sent over the output bus in proper endian domain format. Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet. The novel system is well suited to process arbitrarily sized data packets as well as data packets starting at arbitrary byte boundaries.

摘要翻译： 一种用于转换在两个总线接口之间传输的数据分组的端序域转换电路。 该新颖系统有利地消除了对电路的写入数据路径内的大位开关的任何要求。 相反，endian转换智能被放置在读取数据路径中。 从输入数据分组单独接收双字（双字），字节并行存储到几个不同的先进先出（FIFO）存储器的相同字节位置。 在一个示例中，双字为32位，使用的FIFO存储器数为4。 以这种方式接收整个输入数据分组，增加每个双字的FIFO存储器的写入地址。 根据所需的字节序转换类型，如果根本不存在本发明的字节序转换控制电路，则控制四个典型的FIFO存储器（经由读指针）读取的方式以及它们的数据在 输出总线产生输出数据。 在一个实施例中，在输出总线上产生字节流。 或者，双字通过输出总线以适当的字符串格式发送。 位于数据包头部中的数据描述符定义输入数据包的系统存储器中的端序输入域格式，预期端输出域格式，数据包大小和起始地址。 该新颖的系统非常适合于处理任意大小的数据分组以及从任意字节边界开始的数据分组。

公开(公告)号：US5933610A

公开(公告)日：1999-08-03

申请号：US718086

申请日：1996-09-17

申请人： Peter Chambers ,  Gabriel Roland Munguia

发明人： Peter Chambers ,  Gabriel Roland Munguia

IPC分类号： G06F13/364 ,  G06F13/362

CPC分类号： G06F13/364

摘要： A predictive arbitration system for interfacing a plurality of peripheral component interconnect (PCI) agents coupled to a first PCI bus with a second PCI bus. In one embodiment, the present predictive arbitration system includes a first PCI bus adapted to transmit data signals. A plurality of PCI agents are coupled to the first PCI bus. A predictive arbiter is coupled to both the first PCI bus and a second PCI bus. The predictive arbiter is also coupled to the plurality of PCI agents. The predictive arbiter is configured to receive requests for access to the first or second PCI bus from any of the plurality of PCI agents. The predictive arbiter, upon receiving requests for access, transmits one of the requests to a second arbiter coupled to the second PCI bus, wherein the selected and transmitted request originates from a selected one of the plurality of PCI agents. The predictive arbiter is also adapted to receive a grant signal from the second arbiter in response to the selected and transmitted request. The predictive arbiter further comprises a predictive arbitration system for enabling a grant line coupled to the selected one of the plurality of PCI agents before the grant signal is received from the second arbiter.

摘要翻译： 用于将耦合到第一PCI总线与第二PCI总线的多个外围组件互连（PCI）代理接口的预测仲裁系统。 在一个实施例中，本预测仲裁系统包括适于发送数据信号的第一PCI总线。 多个PCI代理耦合到第一PCI总线。 预测仲裁器耦合到第一PCI总线和第二PCI总线两者。 预测仲裁器还耦合到多个PCI代理。 预测仲裁器被配置为从多个PCI代理中的任何一个接收对第一或第二PCI总线的访问请求。 预测仲裁器在接收到访问请求时将其中一个请求发送到耦合到第二PCI总线的第二仲裁器，其中所选择和发送的请求源自所选择的多个PCI代理中的一个。 预测仲裁器还适于响应于所选择和发送的请求从第二仲裁器接收授权信号。 预测仲裁器还包括预测仲裁系统，用于在从第二仲裁器接收到授权信号之前启用耦合到所选择的多个PCI代理之一的授权线。

公开(公告)号：US5825199A

公开(公告)日：1998-10-20

申请号：US792712

申请日：1997-01-30

申请人： Roger Shelton ,  Peter Chambers

发明人： Roger Shelton ,  Peter Chambers

IPC分类号： H03K19/173

CPC分类号： H03K19/1733

摘要： A reprogrammable state machine which allows the state flow and control outputs to be reprogrammed without requiring modification of the state machine. The reprogrammable state machine uses a reprogrammable logic unit to generate the state transitions and output transitions for each state of the reprogrammable state machine. A memory control unit is used to program the state machine reprogrammable logic unit with default settings for the state transitions and output transitions for each state of the reprogrammable state machine. The memory control unit is also used to reprogram the state machine reprogrammable logic unit with modified settings for the state transitions and output transitions for each state of the reprogrammable state machine which needs to be modified.

摘要翻译： 一种可重复编程状态机，允许状态流量和控制输出重新编程，无需修改状态机。 可再编程状态机使用可重编程逻辑单元来产生可再编程状态机的每个状态的状态转换和输出转换。 存储器控制单元用于对可再编程状态机的每个状态的状态转换和输出转换的默认设置来对状态机可编程逻辑单元进行编程。 存储器控制单元还用于对需要修改的可再编程状态机的每个状态的状态转换和输出转换的修改设置对状态机可编程逻辑单元进行重新编程。

公开(公告)号：US5809333A

公开(公告)日：1998-09-15

申请号：US627988

申请日：1996-04-08

申请人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

发明人： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC分类号： G06F13/28 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F13/28

摘要： The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.

摘要翻译： 本发明是具有外围设备总线母盘的台式个人计算机（PC）系统。 该系统有四个主要元件：直接存储器访问（DMA）控制器，硬件状态机，总线控制器和设备控制器。 设备控制器可以是IDE硬盘控制器，其能够以间歇方式产生长数据流，其中任何单个数据流被定向到多个不同的主机存储器位置。 设备控制器还可以是ECP并行端口控制器，其通过并行总线与多个不同的外围设备进行接口，其中每个外围设备作为独立和独立的数据路径出现在系统中。