公开(公告)号：US09496250B2

公开(公告)日：2016-11-15

申请号：US14563097

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: G06F17/50 ,  H01L27/02 ,  H01L29/735 ,  H01L21/762 ,  H01L29/73 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5072 ,  H01L21/76224 ,  H01L27/082 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7371

Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.

Abstract translation: 双极结型晶体管的设计和制造方法。 基于给定的电流增益确定双极结晶体管的器件区域的预定尺寸。 确定要在衬底中形成以包围器件区域的多个沟槽隔离区域的沟槽隔离布局。 沟槽隔离区域在沟槽隔离布置中相对于彼此横向隔开，以便设定器件区域的预定尺寸。 确定互连布局，其指定与双极结型晶体管的端子耦合的一个或多个触点。 通过确定沟槽隔离布局，互连布局中的一个或多个触点的规格不变。

公开(公告)号：US20160163685A1

公开(公告)日：2016-06-09

申请号：US14563097

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L27/02 ,  H01L29/735 ,  H01L21/762 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5063 ,  G06F17/5072 ,  H01L21/76224 ,  H01L27/082 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/735 ,  H01L29/7371

Abstract: Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout.

Abstract translation: 双极结型晶体管的设计和制造方法。 基于给定的电流增益确定双极结晶体管的器件区域的预定尺寸。 确定要在衬底中形成以围绕器件区域的多个沟槽隔离区域的沟槽隔离布局。 沟槽隔离区域在沟槽隔离布置中相对于彼此横向隔开，以便设定器件区域的预定尺寸。 确定互连布局，其指定与双极结型晶体管的端子耦合的一个或多个触点。 通过确定沟槽隔离布局，互连布局中的一个或多个触点的规格不变。

公开(公告)号：US20180286968A1

公开(公告)日：2018-10-04

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

CPC classification number: H01L29/732 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US20180269295A1

公开(公告)日：2018-09-20

申请号：US15458482

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Alvin J. Joseph ,  John J. Ellis-Monaghan

IPC: H01L29/423 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/78 ,  H01L21/768 ,  H01L23/48 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42376 ,  H01L21/26513 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28167 ,  H01L21/31111 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609

Abstract: Device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor. A first dielectric layer is formed, and a second dielectric layer are formed on the first dielectric layer. An opening is formed that extends vertically through the first and second dielectric layers. After the first opening is formed, the second dielectric layer is laterally recessed relative to the first dielectric layer with a selective etching process, which widens a portion of the opening extending vertically through the second dielectric layer relative to a portion of the opening extending vertically through the first dielectric layer. After the second dielectric layer is laterally recessed, a gate electrode is formed that includes a narrow section in the portion of the opening extending vertically through the first dielectric layer and a wide section in the portion of the opening extending vertically through the second dielectric layer.

公开(公告)号：US20170330790A1

公开(公告)日：2017-11-16

申请号：US15152797

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L21/84 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/66 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02271 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/66 ,  H01L27/1248 ,  H01L29/78654

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US09231087B2

公开(公告)日：2016-01-05

申请号：US14677303

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.