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公开(公告)号：US20180336034A1
公开(公告)日：2018-11-22
申请号：US15597757
申请日：2017-05-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Craig Warner , Qiong Cai , Paolo Faraboschi , Gregg B Lesartre
IPC: G06F9/30 , G06F12/0804 , G06F12/0875 , G06F15/78 , G06F12/128
CPC classification number: G06F9/30185 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30076 , G06F9/30181 , G06F12/0804 , G06F12/0875 , G06F12/128 , G06F15/7825 , G06F2212/452 , G06F2212/60 , G06F2212/69
Abstract: In one example in accordance with the present disclosure, a compute engine block may comprise a data port connecting a processing core to a data cache, wherein the data port receives requests for accessing a memory and a data communication pathway to enable servicing of data requests of the memory. The processing core may be configured to identify a value in a predetermined address range of a first data request and adjust the bit size of a load instruction used by the processing core when a first value is identified.
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公开(公告)号：US10108351B2
公开(公告)日：2018-10-23
申请号：US15190276
申请日：2016-06-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Qiong Cai , Paolo Faraboschi , Cong Xu , Ping Chi , Sai Rahul Chalamalasetti , Andrew C. Walton
IPC: G06F3/06
Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
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公开(公告)号：US09792182B2
公开(公告)日：2017-10-17
申请号：US13755664
申请日：2013-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Sudarsun Kannan , Paolo Faraboschi , Moray McLaren , Dejan S. Milojicic , Robert Schreiber
CPC classification number: G06F11/1438 , G06F2201/82
Abstract: A technique includes generating a checkpoint for an application that is executing on a plurality of nodes of a distributed computing system. Forming the checkpoint includes selectively regulating communication of data from the plurality of nodes to a storage subsystem based at least in part on a replication of the data among the nodes.
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公开(公告)号：US20170220488A1
公开(公告)日：2017-08-03
申请号：US15500460
申请日：2015-03-06
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Rajeev Balasubramonian , Naveen Muralimanohar , Gregg B. Lesartre , Paolo Faraboschi , Jishen Zhao
CPC classification number: G06F12/1408 , G06F3/0619 , G06F3/0623 , G06F3/064 , G06F3/0673 , G06F11/1012 , G06F11/1044 , G06F2212/1052 , G06F2212/402 , H03M7/30 , H03M7/6047 , H03M13/09
Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.
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公开(公告)号：US20170220257A1
公开(公告)日：2017-08-03
申请号：US15500754
申请日：2015-03-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Rajeev Balasubramonian , Gregg B. Lesartre , Robert Schreiber , Jishen Zhao , Naveen Muralimanohar , Paolo Faraboschi
CPC classification number: G06F3/064 , G06F3/061 , G06F3/0659 , G06F3/0683 , G06F11/1012 , G06F12/0223 , G06F12/1408 , G06F2212/401 , G11C7/1006 , G11C7/22
Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.
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Patent Agency Ranking
公开(公告)号：US12242966B2
公开(公告)日：2025-03-04
申请号：US18528935
申请日：2023-12-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , John Paul Strachan , Sergey Serebryakov
Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
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公开(公告)号：US20240419490A1
公开(公告)日：2024-12-19
申请号：US18816471
申请日：2024-08-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dejan S. Milojicic , Kimberly Keeton , Paolo Faraboschi , Cullen E. Bash
Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.
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公开(公告)号：US20240406251A1
公开(公告)日：2024-12-05
申请号：US18494960
申请日：2023-10-26
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Harumi Kuno , John L. Byrne , Paolo Faraboschi , Sharad Singhal
Abstract: In some examples, a system having a plurality of computer nodes receives a command based on program code of a program being developed in an interactive programming session. The system distributes data items from a network-attached memory to a distributed data object having data in node memories of the plurality of computer nodes. A dataset manager performs an operation specified by the command on the distributed data object, the operation executed in parallel on the plurality of computer nodes. The dataset manager produces derived data generated by the operation on the distributed data object, the derived data accessible by a programmer in the interactive programming session.
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公开(公告)号：US20240112029A1
公开(公告)日：2024-04-04
申请号：US18528935
申请日：2023-12-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , John Paul Strachan , Sergey Serebryakov
CPC classification number: G06N3/08 , G11C13/0069 , G11C2213/77
Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
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公开(公告)号：US11119941B2
公开(公告)日：2021-09-14
申请号：US15799153
申请日：2017-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Paolo Faraboschi , Dejan S. Milojicic , Kirk M. Bresniker
IPC: G06F12/14 , G06F12/1027 , G06F12/1009
Abstract: According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.
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