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公开(公告)号：US10565037B2
公开(公告)日：2020-02-18
申请号：US15847067
申请日：2017-12-19
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Charles Johnson , Mesut Kuscu , Onkar Patil , James Hyungsun Park , Harumi Kuno , Robert Schreiber
Abstract: A high performance computing system that includes a shared fabric memory and a plurality of processors is disclosed. A first processor is coupled to a local storage and executes a first process that, in combination with other processes, causes the plurality of processors to perform certain actions including transferring, from the shared fabric memory to the local storage, a first value corresponding to a first cell of a first set of cells and a first sweep of a stencil code. The actions further include transferring, from a first logical partition in the shared fabric memory associated with the first cell to the local storage, a second value corresponding to a second cell related to the first cell and not in the first set of cells. Further, these actions include updating, by the first process, the first value based on at least the first value and the second value.
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公开(公告)号：US09575542B2
公开(公告)日：2017-02-21
申请号：US13755527
申请日：2013-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Doe Hyun Yoon , Moray McLaren , Dejan S. Milojicic , Robert Schreiber , Norman Paul Jouppi
CPC classification number: G06F1/324 , G06F1/3206 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
Abstract: A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.
Abstract translation: 功率管理模块可以基于针对每个操作模式确定的应用性能和总计算机系统功耗，来选择计算机系统中的硬件组件的多种不同操作模式之一。
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公开(公告)号：US09846653B2
公开(公告)日：2017-12-19
申请号：US15120357
申请日：2014-02-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jichuan Chang , Doe Hyun Yoon , Robert Schreiber
IPC: G06F12/08 , G06F12/0891 , G06F12/0862
CPC classification number: G06F12/0891 , G06F12/0862 , G06F2212/2024 , G06F2212/60 , G06F2212/6026
Abstract: Write operations on main memory comprise predicting a last write in a dirty cache line. The predicted last write indicates a predicted pattern of the dirty cache line before the dirty cache line is evicted from a cache memory. Further, the predicted pattern is compared with a pattern of original data bits stored in the main memory for identifying changes to be made in the original data bits. Based on the comparison, an optimization operation to be performed on the original data bits is determined. The optimization operation modifies the original data bits based on the predicted pattern of a last write cache line before the last write cache line is evicted from the cache memory.
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公开(公告)号：US10698878B2
公开(公告)日：2020-06-30
申请号：US15556238
申请日：2015-03-06
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Stanko Novakovic , Kimberly Keeton , Paolo Faraboschi , Robert Schreiber
IPC: G06F16/23 , G06F16/901 , G06F16/27
Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
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公开(公告)号：US20190187924A1
公开(公告)日：2019-06-20
申请号：US15847067
申请日：2017-12-19
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Charles Johnson , Mesut Kuscu , Onkar Patil , James Hyungsun Park , Harumi Kuno , Robert Schreiber
IPC: G06F3/06
Abstract: A high performance computing system that includes a shared fabric memory and a plurality of processors is disclosed. A first processor is coupled to a local storage and executes a first process that, in combination with other processes, causes the plurality of processors to perform certain actions including transferring, from the shared fabric memory to the local storage, a first value corresponding to a first cell of a first set of cells and a first sweep of a stencil code. The actions further include transferring, from a first logical partition in the shared fabric memory associated with the first cell to the local storage, a second value corresponding to a second cell related to the first cell and not in the first set of cells. Further, these actions include updating, by the first process, the first value based on at least the first value and the second value.
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Patent Agency Ranking
公开(公告)号：US20180025043A1
公开(公告)日：2018-01-25
申请号：US15556238
申请日：2015-03-06
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Stanko Novakovic , Kimberly Keeton , Paolo Faraboschi , Robert Schreiber
IPC: G06F17/30
CPC classification number: G06F16/2358 , G06F16/273 , G06F16/9024
Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
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公开(公告)号：US09710335B2
公开(公告)日：2017-07-18
申请号：US14785421
申请日：2013-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Doe Hyun Yoon , Terence P. Kelly , Jichuan Chang , Naveen Muralimanohar , Robert Schreiber , Parthasarathy Ranganathan
CPC classification number: G06F11/1451 , G06F3/0614 , G06F3/0628 , G06F11/1072 , G06F11/1435 , G06F11/1471 , G06F2201/84 , G11C29/52
Abstract: According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.
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公开(公告)号：US10254988B2
公开(公告)日：2019-04-09
申请号：US15500754
申请日：2015-03-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Rajeev Balasubramonian , Gregg B. Lesartre , Robert Schreiber , Jishen Zhao , Naveen Muralimanohar , Paolo Faraboschi
Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.
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公开(公告)号：US09792182B2
公开(公告)日：2017-10-17
申请号：US13755664
申请日：2013-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Sudarsun Kannan , Paolo Faraboschi , Moray McLaren , Dejan S. Milojicic , Robert Schreiber
CPC classification number: G06F11/1438 , G06F2201/82
Abstract: A technique includes generating a checkpoint for an application that is executing on a plurality of nodes of a distributed computing system. Forming the checkpoint includes selectively regulating communication of data from the plurality of nodes to a storage subsystem based at least in part on a replication of the data among the nodes.
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公开(公告)号：US20170220257A1
公开(公告)日：2017-08-03
申请号：US15500754
申请日：2015-03-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Rajeev Balasubramonian , Gregg B. Lesartre , Robert Schreiber , Jishen Zhao , Naveen Muralimanohar , Paolo Faraboschi
CPC classification number: G06F3/064 , G06F3/061 , G06F3/0659 , G06F3/0683 , G06F11/1012 , G06F12/0223 , G06F12/1408 , G06F2212/401 , G11C7/1006 , G11C7/22
Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.
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