公开(公告)号：US12030312B2

公开(公告)日：2024-07-09

申请号：US18448794

申请日：2023-08-11

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  James Michael Gardner ,  Scott A. Linn

IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

CPC classification number: B41J2/04536 ,  B41J2/04541 ,  B41J2/04555 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/04586 ,  G06F3/1293 ,  G06F13/1668 ,  G11C7/1069 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/105

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20230057710A1

公开(公告)日：2023-02-23

申请号：US18045258

申请日：2022-10-10

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Erik D. Ness ,  James Michael Gardner

IPC: B41J2/045

Abstract: In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.

公开(公告)号：US20230034348A1

公开(公告)日：2023-02-02

申请号：US17961476

申请日：2022-10-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  James Michael Gardner ,  Scott A. Linn

IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20210354444A1

公开(公告)日：2021-11-18

申请号：US16479822

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a circuit for use with a memory element and a nozzle for outputting fluid, includes a data line, a fire line, and a selector responsive to the data line to select the memory element or the nozzle. The selector is to select the memory element responsive to the data line having a first value, and to select the nozzle responsive to the data line having a second value different from the first value. The fire line is to control activation of the nozzle in response to the nozzle being selected by the selector, and to communicate data of the memory element in response to the memory element being selected by the selector.

公开(公告)号：US10800168B2

公开(公告)日：2020-10-13

申请号：US16337837

申请日：2016-10-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: B41J2/045 ,  B41J2/175 ,  G11C11/4094 ,  G11C7/12

Abstract: In some examples, a control apparatus for a fluid ejection device includes a plurality of selectors controllable by an input control signal to produce signals for selecting respective nozzles of the fluid ejection device, where a first selector is responsive to the input control signal propagated over a first signal path to turn on a device in the first selector, and a second selector is responsive to the input control signal to perform a different task. A memory encoder is to select a memory location in the memory, the memory encoder responsive to the input control signal propagated over a second signal path to turn on a device in the memory encoder, where signal loading of the second signal path is isolated from signal loading of the first signal path.

公开(公告)号：US10556445B2

公开(公告)日：2020-02-11

申请号：US16095001

申请日：2016-07-15

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Jerrin Pathrose Vareed ,  Boon Bing Ng

IPC: B41J2/35 ,  B41J2/355 ,  B41J2/135 ,  B41J2/335 ,  B41J29/38

Abstract: Examples of a printhead assembly comprising an Erasable Programmable Read-only Memory (EPROM) having a predefined number of banks, with EPROM cells arranged in rows and columns in each of the banks are described. In one example, the printhead assembly comprises a shift register to generate, in consecutive shift register cycles, a row select signal, column select signal, and bank select signal to select a row, column, and bank, respectively, corresponding to an EPROM cell. A row select signal bus, column select signal bus and bank select signal bus is included in the printhead assembly to provide the row select signal, column select signal, and bank select signal, respectively, to the EPROM cell during the respective shift register cycles.

公开(公告)号：US10532579B2

公开(公告)日：2020-01-14

申请号：US15761621

申请日：2015-11-10

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Patrick Leonard ,  Raymond Connolly

IPC: B41J2/175 ,  G01F23/26 ,  B41J2/14

Abstract: The present subject matter relates to printhead-integrated ink level sensor (PILS) system. In an example implementation, the PILS system includes a sense capacitor plate in a fluid sensing chamber to sense a level of fluid in the fluid sensing chamber. The fluid sensing chamber is in fluid communication with a fluid reservoir of the printhead to receive fluid from the fluid reservoir. The sense capacitor plate includes at least one slot. The PILS system further includes at least one central clearing resistor and at least one peripheral clearing resistor to clear the fluid sensing chamber of the fluid. The central clearing resistor is provided in the at least one slot of the sense capacitor plate. The at least one peripheral resistor is provided in the fluid sensing chamber surrounding the sense capacitor plate.

公开(公告)号：US10403362B2

公开(公告)日：2019-09-03

申请号：US16255361

申请日：2019-01-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  G11C16/14 ,  G11C8/12 ,  G11C16/08 ,  B41J2/175 ,  G11C19/28 ,  G11C19/00

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US20190156892A1

公开(公告)日：2019-05-23

申请号：US16255361

申请日：2019-01-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  G11C19/28 ,  B41J2/175 ,  G11C8/12 ,  G11C16/08

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US10236063B2

公开(公告)日：2019-03-19

申请号：US15986531

申请日：2018-05-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  G11C8/12 ,  G11C16/08 ,  B41J2/175 ,  G11C19/28 ,  G11C16/14 ,  G11C19/00

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.