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    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    21.
    发明申请
    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 审中-公开
    处理器使用较少的硬件和指令转换设备减少指令类型的数量

    公开(公告)号：US20050091478A1

    公开(公告)日：2005-04-28

    申请号：US10617506

    申请日：2003-07-11

    申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/45 ,  G06F9/00

    CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

    摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

    摘要翻译： 解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥， 第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

    Instruction converting apparatus using parallel execution code
    22.
    再颁专利
    Instruction converting apparatus using parallel execution code 有权
    指令转换装置采用并行执行码

    公开(公告)号：USRE41751E1

    公开(公告)日：2010-09-21

    申请号：US10720030

    申请日：2003-11-24

    申请人： Taketo Heishi ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Shuichi Takayama ,  Kensuke Odani

    发明人： Taketo Heishi ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Shuichi Takayama ,  Kensuke Odani

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30149 ,  G06F9/30167 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885

    摘要： A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.

    摘要翻译： 处理器可以解码具有等于一个单位字段的字长度和长度等于两个单位字段的长指令的短指令。 每种指令的操作码被布置到分配给指令的第一单位字段中。 由处理器并行执行的指令数是s。 当短指令与长指令的比率为s-1：1时，将s-1短指令分配给并行执行代码中的s-1tA单位字段的第一个单位字段，并将长指令分配给sth 单位字段到同一个并行执行代码中的（s + k-1）个单位字段。

    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    23.
    发明授权
    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 有权
    处理器使用较少的硬件和指令转换设备减少指令类型的数量

    公开(公告)号：US06606703B2

    公开(公告)日：2003-08-12

    申请号：US09756068

    申请日：2001-01-08

    申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    IPC分类号： G06F1500

    CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

    摘要： Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.

    摘要翻译： 处理器和指令转换装置，包括当使用条件指令时减少指令类型数量和处理器硬件比例的技术。 处理器包括凝视保持单元，获取单元，解码单元，判断单元和执行单元。 当由解码单元解码时，判断单元判断状态保持单元更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态。 当判断为肯定时，执行单元执行由解码单元解码的第一条件指令中由操作码指定的操作。 指令集被分配具有第一状态条件的第一条件指令，该第一状态条件与用于未分配的第二条件指令的第二状态条件相互排斥，所述第二状态条件具有相同的操作代码。

    Constant reconstructing processor that execute an instruction using an operand divided between instructions
    24.
    发明授权
    Constant reconstructing processor that execute an instruction using an operand divided between instructions 失效
    使用在指令之间划分的操作数来执行指令的恒定重构处理器

    公开(公告)号：US06195740B1

    公开(公告)日：2001-02-27

    申请号：US09124659

    申请日：1998-07-29

    申请人： Taketo Heishi ,  Nobuo Higaki ,  Akira Tanaka ,  Tetsuya Tanaka ,  Shuichi Takayama ,  Kensuke Odani ,  Shinya Miyaji

    发明人： Taketo Heishi ,  Nobuo Higaki ,  Akira Tanaka ,  Tetsuya Tanaka ,  Shuichi Takayama ,  Kensuke Odani ,  Shinya Miyaji

    IPC分类号： G06F930

    CPC分类号： G06F9/30167 ,  G06F9/30156 ,  G06F9/30163 ,  G06F9/3822 ,  G06F9/3853

    摘要： A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of the instruction stored in the instruction register 10; a constant storage unit including a storage region; a constant register control unit 32 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register 36, transfers the constant from the instruction register 10 to the constant storage unit 36; and a constant register output unit 41 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register 36 with the piece of the operand.

    摘要翻译： 用于解码和执行指令的处理器包括：用于存储指令的指令寄存器10; 格式解码器21，用于对存储在指令寄存器10中的指令的P0.0字段11中的格式代码进行解码; 包括存储区域的恒定存储单元; 常数寄存器控制单元32，当格式解码器21参考格式代码并解码时，操作字段包括要存储在常数寄存器36中的常数时，将常数从指令寄存器10传送到恒定存储单元 36; 以及常数寄存器输出单元41，当格式解码器21参考格式代码并解码时，操作字段包括表示应该执行的操作的操作码和应该用于操作的操作数 ，将存储在常数寄存器36中的常数与操作数的段连接起来。

    Constant reconstruction processor that supports reductions in code size and processing time
    25.
    发明授权
    Constant reconstruction processor that supports reductions in code size and processing time 失效
    恒定重建处理器，支持缩小代码大小和处理时间

    公开(公告)号：US06209080B1

    公开(公告)日：2001-03-27

    申请号：US09124335

    申请日：1998-07-29

    申请人： Taketo Heishi ,  Nobuo Higaki ,  Akira Tanaka ,  Tetsuya Tanaka ,  Shuichi Takayama ,  Kensuke Odani ,  Shinya Miyaji

    发明人： Taketo Heishi ,  Nobuo Higaki ,  Akira Tanaka ,  Tetsuya Tanaka ,  Shuichi Takayama ,  Kensuke Odani ,  Shinya Miyaji

    IPC分类号： G06F930

    CPC分类号： G06F9/30167 ,  G06F9/30163 ,  G06F9/383 ,  G06F9/3853

    摘要： A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361. When the decoding unit 20 finds that the instruction includes a branch operation, the execution unit 30 executes the branch operation using the constant stored in the branching constant register 362. When the decoding unit 20 finds that the instruction includes an arithmetic operation, the execution unit 30 executes the arithmetic operation using the constant stored in the operation constant register 361.

    摘要翻译： 用于基于指令执行操作的处理器包括操作常数寄存器361，分支常数寄存器362，用于解码存储在指令寄存器10中的指令的解码单元20，常数寄存器控制单元32和执行单元30.当 解码单元20发现指令包括要存储在分支常数寄存器362中的常数，常数寄存器控制单元32移位分支常数寄存器362中的当前值并插入要存储的常数，从而存储新常数 在分支常数寄存器362中。当解码单元20发现将常数存储在操作常数寄存器361中时，常数寄存器控制单元32移动操作常数寄存器361中的当前值，并插入要存储的常数 ，从而在操作常数寄存器361中存储新常数。当解码单元20发现指令包括时 分支操作，执行单元30使用存储在分支常数寄存器362中的常数来执行分支操作。当解码单元20发现指令包括算术运算时，执行单元30使用存储在 操作常数寄存器361。

    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions
    26.
    发明授权
    Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 有权
    处理器使用较少的硬件和指令转换设备减少指令类型的数量

    公开(公告)号：US06230258B1

    公开(公告)日：2001-05-08

    申请号：US09144298

    申请日：1998-08-31

    申请人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    发明人： Shuichi Takayama ,  Kensuke Odani ,  Akira Tanaka ,  Nobuo Higaki ,  Masato Suzuki ,  Tetsuya Tanaka ,  Taketo Heishi ,  Shinya Miyaji

    IPC分类号： G06F930

    CPC分类号： G06F9/30058 ,  G06F8/447 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3842

    摘要： An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition. While the judgment unit decision is negative, the conversion unit converts the conversion target instruction sequence into an instruction sequence including a conditional instruction with a condition that is mutually exclusive with the predetemiined condition.

    摘要翻译： 一种用于将不包括条件指令的指令序列转换成包括条件指令的指令序列的指令转换装置和方法，其中条件指令包括当条件满足时由处理器执行的条件和操作代码两者。 获取单元接收不包括条件指令的指令序列，由此当满足预定条件时，指令序列检测单元检测到将不同转移对象传送到同一存储资源的转换目标指令序列。 判断单元判断专用处理器的指令集是否被分配条件指令，该条件指令包括与前提条件相同的条件，由此转换单元然后可以将转换目标指令序列转换为包括具有预定条件的条件指令的指令序列。 当判断单元判定为否定时，转换单元将转换目标指令序列转换成具有条件的条件指令的指令序列，该条件与预先设定的条件相互排斥。

    Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program
    28.
    发明授权
    Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program 失效
    降低循环流水线处理延迟和存储优化程序的计算机可读存储介质的优化装置

    公开(公告)号：US06993756B2

    公开(公告)日：2006-01-31

    申请号：US09798490

    申请日：2001-03-02

    申请人： Hajime Ogawa ,  Shuichi Takayama

    发明人： Hajime Ogawa ,  Shuichi Takayama

    IPC分类号： G06F9/45

    CPC分类号： G06F8/452 ,  G06F8/4452

    摘要： An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.

    摘要翻译： 优化装置能够提高循环的执行效率，该循环在循环的连续迭代之间包括循环进位依赖性。 例如，由一次迭代产生的值在紧随其后的迭代中使用。 当算术表达式“a [i + 1] = a [i] * 3 + 2;” 被包含在循环体中，并且由算术表达式“a [i + 1] = a [i] * 3 + 2]得到的值; 在一次迭代中，在下一次迭代中使用，在循环的流水线处理中出现执行延迟。 这里，算术表达式“a [i + 1] = a [i] * 3 + 2;” 被转换成算术表达式“a [i + 4] = a [i] * 81 + 80;” 扩大依赖距离。 通过这样做，可以减少执行延迟。