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187 条记录 (耗时 0.038 秒)

    Dishing-Free Gap-Filling with Multiple CMPs
    21.
    发明申请
    Dishing-Free Gap-Filling with Multiple CMPs 有权
    无间隙填充多个CMP

    公开(公告)号：US20110227189A1

    公开(公告)日：2011-09-22

    申请号：US13151666

    申请日：2011-06-02

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiun-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiun-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L27/04

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

    摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。 该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

    Photo alignment mark for a gate last process
    24.
    发明授权
    Photo alignment mark for a gate last process 有权
    最后一个进程的照片对齐标记

    公开(公告)号：US08598630B2

    公开(公告)日：2013-12-03

    申请号：US12470333

    申请日：2009-05-21

    申请人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

    发明人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

    IPC分类号： H01L23/52

    CPC分类号： H01L23/544 ,  H01L21/31051 ,  H01L21/823828 ,  H01L23/585 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.

    摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，第一和第二区域彼此隔离，形成在第一区域中的多个晶体管，形成在第二区域中的对准标记， 对准标记具有在第一方向上的多个有效区域，以及形成在所述对准标记上的伪栅极结构，所述伪栅极结构在与所述第一方向不同的第二方向上具有多条线。

    Method for semiconductor device performance enhancement
    25.
    发明授权
    Method for semiconductor device performance enhancement 有权
    半导体器件性能提高的方法

    公开(公告)号：US07632729B2

    公开(公告)日：2009-12-15

    申请号：US11527616

    申请日：2006-09-27

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

    摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

    摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

    Reducing Device Performance Drift Caused by Large Spacings Between Action Regions
    26.
    发明申请
    Reducing Device Performance Drift Caused by Large Spacings Between Action Regions 有权
    减少行动区域之间大间距引起的设备性能漂移

    公开(公告)号：US20090273052A1

    公开(公告)日：2009-11-05

    申请号：US12175976

    申请日：2008-07-18

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

    IPC分类号： H01L21/322 ,  H01L27/10

    CPC分类号： H01L21/823475 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7846

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

    摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。 第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。 第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。 该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

    Semiconductor Device with both I/O and Core Components and Method of Fabricating Same
    27.
    发明申请
    Semiconductor Device with both I/O and Core Components and Method of Fabricating Same 有权
    具有I / O和核心组件的半导体器件及其制造方法

    公开(公告)号：US20080315320A1

    公开(公告)日：2008-12-25

    申请号：US11766425

    申请日：2007-06-21

    申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

    发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

    IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

    摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

    摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

    Layout methods of integrated circuits having unit MOS devices
    28.
    发明申请
    Layout methods of integrated circuits having unit MOS devices 有权
    具有单位MOS器件的集成电路的布局方法

    公开(公告)号：US20080296691A1

    公开(公告)日：2008-12-04

    申请号：US11807654

    申请日：2007-05-30

    申请人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

    发明人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0207 ,  H01L27/11 ,  H01L27/1104

    摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

    摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。