公开(公告)号：US20250124879A1

公开(公告)日：2025-04-17

申请号：US18687988

申请日：2022-11-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang SHANG ,  Jianchao ZHU ,  Jiangnan LU ,  Yu FENG ,  Rui XU ,  Xing YAO

IPC: G09G3/3266

Abstract: Provided are a display panel, a display apparatus and a method for driving the display panel. The display panel includes: multiple gate lines; and multiple shift register units, a target shift register unit of the shift register units includes: a frame trigger selecting circuit and a gate driving circuit; the frame trigger selecting circuit is coupled to a frame trigger input terminal and frame starting signal terminals corresponding to N cascade groups, and outputs, in response to an nth turn-on signal of N turn-on signals corresponding to an nth cascade group, a starting signal input to the frame trigger input terminal to a frame starting signal terminal corresponding to the nth cascade group; 1≤n≤N, and n is an integer; the nth cascade group scans the gate lines coupled thereto line by line after the frame starting signal terminal corresponding thereto receives the starting signal.

公开(公告)号：US20250095536A1

公开(公告)日：2025-03-20

申请号：US18290015

申请日：2022-11-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Donghui ZHAO ,  Pan XU ,  Ying HAN ,  Xing ZHANG ,  Chengyuan LUO ,  Guangshuang LV ,  Xing YAO ,  Dandan ZHOU ,  Miao LIU

IPC: G09G3/20

Abstract: Provided is a pixel drive circuit. The pixel drive circuit includes a plurality of scan drive circuits transmitting gate drive signals to pixels, a plurality of emission drive circuits transmitting emission control signals to the pixels, a plurality of compensation drive circuits transmitting compensation signals to the pixels, and a plurality of reset drive circuits transmitting reset signals to the pixels, which are all cascaded in a pixel column direction. In addition, the scan drive circuit, the emission drive circuit, the compensation drive circuit, and the reset drive circuit corresponding to the same row of pixels are arranged sequentially along a pixel row direction, the scan drive circuit being disposed farthest away from the pixels. Moreover, among signal lines coupled to the pixel drive circuit, a plurality of signal lines is overlapped with each other, and cutouts are provided at the overlapping portions of the plurality of signal lines.

公开(公告)号：US20240304266A1

公开(公告)日：2024-09-12

申请号：US18245030

申请日：2022-05-26

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan LU ,  Guangliang SHANG ,  Jianchao ZHU ,  Zhenzhen SHAN ,  Xing YAO

IPC: G11C19/28 ,  G09G3/3225

CPC classification number: G11C19/287 ,  G09G3/3225 ,  G09G2300/0426 ,  G09G2310/0286

Abstract: A shift register unit includes: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node; where a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal.

公开(公告)号：US20210193027A1

公开(公告)日：2021-06-24

申请号：US17086097

申请日：2020-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang ZHENG ,  Dongni LIU ,  Minghua XUAN ,  Zhenyu ZHANG ,  Li XIAO ,  Liang CHEN ,  Hao CHEN ,  Guangliang SHANG ,  Lijun YUAN ,  Xing YAO

IPC: G09G3/32

Abstract: A shift register includes an input sub-circuit, a control sub-circuit, an output sub-circuit and a reset sub-circuit. The input sub-circuit is configured to transmit an input signal from an input signal terminal to a pull-up node. The control sub-circuit is configured to transmit a clock signal from a clock signal terminal to the control node. The output sub-circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a first output signal terminal, and to transmit a first voltage signal from a first voltage signal terminal to the first output signal terminal. The reset sub-circuit is configured to transmit the second voltage signal to the control node to reset the control node, and to transmit a third voltage signal from the third voltage signal terminal to the pull-up node to reset the pull-up node.

公开(公告)号：US20200227006A1

公开(公告)日：2020-07-16

申请号：US16633026

申请日：2019-05-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xing YAO ,  Mingfu HAN ,  Guangliang SHANG ,  Hao ZHU ,  Yifang CHU ,  Yunsik IM

IPC: G09G5/10 ,  G09G3/20

Abstract: The present disclosure provides a compensation method, compensation device, and a display device. The compensation method includes: adjusting charging time for multiple areas of the display screen so that the charging time for each area is positively related to a distance from the area to a data voltage input terminal; comparing a first grayscale value before compensation of a sub-pixel in an i-th row and j-th column with a second grayscale value input to a sub-pixel in an (i−1)-th row and j-th column; searching a corresponding grayscale compensation parameter from a grayscale compensation parameter table according to the first grayscale value and the second grayscale value; compensating the first grayscale value by the grayscale compensation parameter to obtain a third grayscale value; and inputting the third grayscale value to the sub-pixel in the i-th row and j-th column for display.

公开(公告)号：US20200219428A1

公开(公告)日：2020-07-09

申请号：US16515880

申请日：2019-07-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lijun YUAN ,  Xing YAO ,  Guangliang SHANG ,  Haoliang ZHENG ,  Zhenyu ZHANG

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift register circuit according to an embodiment of the present disclosure includes an input sub-circuit and N-stage output sub-circuits. The input sub-circuit is configured to transmit an input signal to a pull up node at a first stage. The output sub-circuit at each stage is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of a pull-up node at the same stage. The output sub-circuit at each stage is further configured to transmit a signal transmitted to an output signal terminal at the same stage to a pull-up node at an immediately subsequent stage under the control of a shift control signal from a shift control signal terminal at the same stage.

公开(公告)号：US20180293956A1

公开(公告)日：2018-10-11

申请号：US15840757

申请日：2017-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xing YAO ,  Seung-Woo HAN ,  Guangliang SHANG ,  Mingfu HAN ,  Haoliang ZHENG ,  Yun-Sik IM

IPC: G09G5/00 ,  G11C19/18 ,  G11C19/28

Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a plurality of shift register units, a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines. The plurality of gate lines crossing the plurality of data lines defines a plurality of pixel regions. Each of the pixel regions is divided into a driving zone and a pixel unit zone. A plurality of the driving zones in a same column constitute at least one unit region and each of the shift register units is disposed in one of the unit regions to provide scanning signals to the gate line connected thereto.

公开(公告)号：US20170270879A1

公开(公告)日：2017-09-21

申请号：US15501265

申请日：2016-07-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Mingfu HAN ,  Seungwoo HAN ,  Guangliang SHANG ,  Hyunsic CHOI ,  Xing YAO ,  Haoliang ZHENG ,  Xue DONG ,  Jungmok JUN ,  Yunsik IM

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

Abstract: The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.

公开(公告)号：US20170039987A1

公开(公告)日：2017-02-09

申请号：US14909661

申请日：2015-07-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xing YAO ,  Yuanbo ZHANG ,  Seungwoo HAN

IPC: G09G5/00 ,  G11C19/28

CPC classification number: G09G5/003 ,  G09G3/20 ,  G09G3/30 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0251 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28

Abstract: A shift register unit includes: a discharging TFT, a source electrode and a drain electrode of which are connected to a first low level signal input end and a pull-up node respectively; and a first discharging control unit connected to a gate electrode of the discharging TFT and configured to output a first control signal to the gate electrode of the discharging TFT between a first and a second time points, so as to enable the discharging TFT to be in an on state and output a first low level signal to the pull-up node, thereby to discharge the pull-up node. The first time point is a time point when the processing of a first frame by the shift register is ended, and the second time point is a time point when the processing of a second frame adjacent to the first frame by the shift register is started.

Abstract translation: 移位寄存器单元包括：放电TFT，源电极和漏电极分别连接到第一低电平信号输入端和上拉节点; 以及第一放电控制单元，连接到放电TFT的栅电极，并且被配置为在第一和第二时间点之间向放电TFT的栅电极输出第一控制信号，以使放电TFT处于 导通状态并将第一低电平信号输出到上拉节点，从而放电上拉节点。 第一时间点是移位寄存器对第一帧的处理结束的时间点，第二时间点是由移位寄存器开始与第一帧相邻的第二帧的处理的时刻。

公开(公告)号：US20160379585A1

公开(公告)日：2016-12-29

申请号：US14906475

申请日：2015-08-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xing YAO ,  Seungwoo HAN ,  Yuanbo Zhang

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021

Abstract: The present invention discloses a Gate-driver-On-Array (GOA) circuit and the driving method thereof and a display device. The GOA circuit comprises a driving module, a low-resolution module and at least two high-resolution modules, the driving module being connected with the low-resolution module and the at least two high-resolution modules respectively; wherein, the driving module is used to output control signal to the low-resolution module and the high-resolution modules; the low-resolution module is used to output a low-resolution signal to at least two rows of pixels under the control of the control signal during low-resolution display; and each high-resolution module is used to output a high-resolution signal to corresponding one row of pixels under the control of the control signal during high-resolution display. The GOA circuit of the present invention may be used to drive multiple rows of pixels and implement the switching between low resolution display and high resolution display.

Abstract translation: 本发明公开了一种栅极驱动器阵列（GOA）电路及其驱动方法和显示装置。 GOA电路包括驱动模块，低分辨率模块和至少两个高分辨率模块，驱动模块分别与低分辨率模块和至少两个高分辨率模块连接; 其中，驱动模块用于将控制信号输出到低分辨率模块和高分辨率模块; 低分辨率模块用于在低分辨率显示期间在控制信号的控制下将低分辨率信号输出到至少两行像素; 并且每个高分辨率模块用于在高分辨率显示期间在控制信号的控制下将高分辨率信号输出到对应的一行像素。 本发明的GOA电路可以用于驱动多行像素并实现低分辨率显示和高分辨率显示之间的切换。