公开(公告)号：US07304507B1

公开(公告)日：2007-12-04

申请号：US11288496

申请日：2005-11-28

申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

IPC分类号： H03K19/00

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.

摘要翻译： 在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。 这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。 相同的方法可以用于在收发器块之间分配其他类型的信号。 例如，该方法可用于分配校准控制信号。

公开(公告)号：US07276937B2

公开(公告)日：2007-10-02

申请号：US11270718

申请日：2005-11-08

申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

IPC分类号： H03K19/177

CPC分类号： G06F1/10 ,  H03K19/177 ,  H03K19/17736

摘要： Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

公开(公告)号：US09246715B1

公开(公告)日：2016-01-26

申请号：US12432136

申请日：2009-04-29

申请人： Allen Chan ,  Wilson Wong ,  Tim Tri Hoang

发明人： Allen Chan ,  Wilson Wong ,  Tim Tri Hoang

IPC分类号： H03K19/094 ,  H04L25/02 ,  H03K19/003

CPC分类号： H04L25/0272 ,  H03K19/00315 ,  H03K19/00361

摘要： A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.

摘要翻译： 一种预加重电路，其包括（1）具有转移检测电路的预加重电压变化补偿（PVVC）引擎和（2）耦合到PVVC引擎的补偿驱动器。 在一个实施例中，补偿驱动器减少由预加重电路提供的预加重中的数据相关电压变化。 在一个实施例中，响应于由PVVC引擎检测到的预定数据模式，补偿驱动器为预加重电路的性能关键电容性节点提供额外的提升。 额外的升压会导致性能关键的电容性节点更快地充电或放电。 在一个实施例中，PVVC引擎还包括耦合到转换检测电路的数字有限脉冲响应（FIR）滤波器。 此外，在一个实施例中，PVVC引擎还包括耦合到数字FIR滤波器的FIR延迟电路和耦合到数字FIR滤波器和FIR延迟电路的同步器电路，其中FIR延迟电路将等待时间延迟到由 转换检测电路和同步器电路将要发送到主驱动器，预加重驱动器和补偿驱动器的数据同步。

公开(公告)号：US08671305B1

公开(公告)日：2014-03-11

申请号：US13175604

申请日：2011-07-01

申请人： Shou-Po Shih ,  Tim Tri Hoang ,  Kazi Asaduzzaman

发明人： Shou-Po Shih ,  Tim Tri Hoang ,  Kazi Asaduzzaman

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： H04B10/6165 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/0083 ,  H04L7/033

摘要： A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit is operable to generate a first phase detection signal based on a data signal and a first periodic signal. The phase frequency detector circuit is operable to generate a second phase detection signal based on second and third periodic signals. The data detection circuit is operable to generate a data detection signal based on the first phase detection signal. A multiplexer circuit is operable to provide one of the first and the second phase detection signals as a selected signal based on the data detection signal. The periodic signal generation circuit is operable to cause adjustments to phases of the first and the second periodic signals based on the selected signal.

摘要翻译： 电路包括相位检测器电路，相位频率检测器电路，数据检测电路，多路复用器电路和时钟信号发生电路。 相位检测器电路可操作以基于数据信号和第一周期信号产生第一相位检测信号。 相位频率检测器电路可操作以基于第二和第三周期信号产生第二相位检测信号。 数据检测电路可操作以基于第一相位检测信号产生数据检测信号。 多路复用器电路可操作以基于数据检测信号提供第一和第二相位检测信号中的一个作为选择的信号。 周期信号产生电路可操作以基于所选择的信号来调整第一和第二周期信号的相位。

公开(公告)号：US08559582B2

公开(公告)日：2013-10-15

申请号：US12881160

申请日：2010-09-13

申请人： Tim Tri Hoang

发明人： Tim Tri Hoang

IPC分类号： H04L7/033

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/183

摘要： A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols.

摘要翻译： 电路包括相位检测电路，相位调整电路和采样电路。 相位检测电路将第一周期信号的相位与第二周期信号的相位进行比较，以产生控制信号。 相位调整电路使得第二周期信号的相位和第三周期信号的相位根据控制信号的变化而变化。 采样器电路对数据信号进行采样，以响应于第三周期信号产生采样数据信号。 电路改变第三周期信号的频率，以对应于基于至少三个数据传输协议的至少三个不同数据速率之间的数据信号的数据速率的变化。

公开(公告)号：US08294500B1

公开(公告)日：2012-10-23

申请号：US12621493

申请日：2009-11-18

申请人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang ,  Van Ton-That

发明人： Vinh Van Ho ,  Tien Duc Pham ,  Tim Tri Hoang ,  Van Ton-That

IPC分类号： H03H11/16

CPC分类号： G06G7/30

摘要： A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

摘要翻译： 相位插值器电路包括耦合以形成差分对的第一和第二晶体管，负载电路，第一组开关电路，第二组开关电路和电流源。 第一组开关电路耦合在第一晶体管和负载电路之间。 第二组开关电路耦合在第二晶体管和负载电路之间。 电流源为差分对提供电流。

公开(公告)号：US08208528B1

公开(公告)日：2012-06-26

申请号：US11955948

申请日：2007-12-13

申请人： Tin H. Lai ,  Sergey Shumarayev ,  Tim Tri Hoang

发明人： Tin H. Lai ,  Sergey Shumarayev ,  Tim Tri Hoang

IPC分类号： H03H7/30

CPC分类号： H04B10/695

摘要： Adaptation convergence in an adaptive dispersion compensation engine (ADCE) of a high-speed serial interface is detected by monitoring the output of the error amplifier of one or more adjustment loops of the ADCE. Adaptation convergence is considered to have been detected upon detection of a predetermined number of transitions in the error amplifier output, each of which occurs within a preselected interval following the previous transition. The detector may be implemented with a timer that times the preselected interval and a counter that counts transitions in the error amplifier output. The timer restarts each time a transition occurs, and the counter outputs a convergence signal when it reaches the predetermined number, but is reset each time the timer reaches the preselected interval. The serial interface may be part of a programmable integrated circuit device and in any case the preselected interval and the predetermined number may be programmable.

摘要翻译： 通过监视ADCE的一个或多个调节回路的误差放大器的输出来检测高速串行接口的自适应色散补偿引擎（ADCE）中的适应收敛。 认为在误差放大器输出中检测到预定数量的转换后已经检测到适应收敛，其中每一个都在先前转换之后的预选间隔内发生。 检测器可以用定时器实现，该定时器乘以预选间隔，而计数器可以对误差放大器输出中的转换进行计数。 定时器在每次转换发生时重新开始计时，当计数器达到预定数量时，计数器输出会聚信号，但每当定时器达到预先选定的时间间隔时，计数器都会被复位。 串行接口可以是可编程集成电路器件的一部分，并且在任何情况下，预选间隔和预定数量可以是可编程的。

公开(公告)号：US08175143B1

公开(公告)日：2012-05-08

申请号：US12037284

申请日：2008-02-26

申请人： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

发明人： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC分类号： H03H7/30

CPC分类号： H04L25/03057 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03745 ,  H04L2025/03783

摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.

摘要翻译： 用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机 以提取用于数字化的参考电平并控制均衡曲线。 参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。 状态机优选是可编程的。 这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

公开(公告)号：US08127215B2

公开(公告)日：2012-02-28

申请号：US13151717

申请日：2011-06-02

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03M13/03

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07920621B2

公开(公告)日：2011-04-05

申请号：US11522284

申请日：2006-09-14

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。