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公开(公告)号：US10691517B2
公开(公告)日：2020-06-23
申请号：US15744043
申请日：2015-07-17
IPC分类号： G06F11/00 , G06Q10/04 , G06F1/3203 , G05B23/02 , G06Q10/06 , G06F11/30 , G06Q10/00 , G01R31/50 , G01R23/02 , G06F11/34
摘要： In one example in accordance with the present disclosure, a method for determining operating frequencies includes receiving a warranty period for a computer component. The method includes determining an operating frequency that will cause a predicted life cycle of the computer component operating at the operating frequency to fall within the warranty period. The method includes setting the computer component to operate at the operating frequency.
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公开(公告)号：US10289423B2
公开(公告)日：2019-05-14
申请号：US15323945
申请日：2014-10-31
发明人： Vincent Nguyen , Chanh V. Hua , Ning Ge , Naveen Muralimanohar
IPC分类号： G06F11/30 , G06F9/4401 , G06F1/3287
摘要： A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.
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公开(公告)号：US10180793B2
公开(公告)日：2019-01-15
申请号：US15420313
申请日：2017-01-31
发明人： Vincent Nguyen , Thierry Fevrier , David Engler
IPC分类号： G06F3/06
摘要： An example device in accordance with an aspect of the present disclosure includes a plurality of memory segments corresponding to at least one memory channel of a computing system that is to receive a memory module. A performance attribute of an Advanced Configuration and Power Interface (ACPI) table is set to indicate performance of at least one of the plurality of memory segments, and is usable for memory allocation by an operating system memory manager.
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公开(公告)号：US20180165238A1
公开(公告)日：2018-06-14
申请号：US15578521
申请日：2015-06-26
摘要： Example implementations relate to a self-tune controller. For example, the self-tune controller may poll, via an out-of-band data stream, low-level operation information about a processor or a bus of a computing system under a present workload. At least some of the low-level operation information may be descriptive of a nature of traffic on the bus. The self-tune controller may program, via an out-of-band control signal, a setting of the computing system for the present workload based on the low-level operation information.
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公开(公告)号：US20180088638A1
公开(公告)日：2018-03-29
申请号：US15273860
申请日：2016-09-23
发明人： Vincent Nguyen , Michael T. Gill
摘要： A method may include assigning a core identifier of an active core to an idle core. After synchronizing the active core and idle core, the active core is inactivated.
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公开(公告)号：US20240364062A1
公开(公告)日：2024-10-31
申请号：US18140476
申请日：2023-04-27
发明人： Ku-Hsu Nien , Vincent Nguyen , Kuan-Wei Chen
CPC分类号： H01R31/06 , H05K1/18 , H05K2201/10189 , H05K2201/10356 , H05K2201/10522
摘要： A cable system includes a printed circuit board (PCB) comprising a set of connector pin pads and a card-side connector, with the card-side connector comprising a housing attached to the PCB and a set of pins. A first subset of the set of pins is soldered on and electrically coupled to the connector pin pads. The cable system includes first and second cables electrically coupled to the card-side connector. The first cable includes a first end soldered onto the connector pin pads to couple to the first subset of the pins and a second end coupled to a first host-side connector. The second cable includes a first end soldered onto a second subset of the set of pins of the card-side connector and a second end coupled to a second host-side connector, thereby facilitating electrical coupling between the card-side connector and the first and second host-side connectors.
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公开(公告)号：US20240064919A1
公开(公告)日：2024-02-22
申请号：US17889198
申请日：2022-08-16
发明人： Vincent Nguyen , Minh H. Nguyen , Kuan-Wei Chen
IPC分类号： H05K7/14
CPC分类号： H05K7/1427
摘要： One aspect of the instant application describes a system that includes a plurality of stacked mezzanine boards communicatively coupled to a motherboard and a metal enclosure enclosing the motherboard and mezzanine boards. A respective mezzanine board can include a number of solder pads, and the metal enclosure can include a plurality of metal strips, a respective metal strip to make contact with a solder pad of a corresponding mezzanine board. The system can further include a logic module positioned on the respective mezzanine board to determine a location of the respective mezzanine board based on a contact pattern between the metal strips and solder pads of the respective mezzanine board.
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公开(公告)号：US20210286744A1
公开(公告)日：2021-09-16
申请号：US16820497
申请日：2020-03-16
发明人： John Norton , Ku-Hsu Nien , Vincent Nguyen , Kuan-WeI Chen
摘要： A system manages communication between a host device and an end device. The system includes a programmable input/output (I/O) port associated with the host device. The host device is connectable through the programmable I/O port and a cable to a plurality of different types of end devices that are respectively associated with different types of protocols. The system further includes a port manager to detect a signal from an end device interface associated with the end device and determine a type of the end device based on the detected signal. The port manager directs the programmable I/O port to present signals that correspond to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.
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公开(公告)号：US10701800B2
公开(公告)日：2020-06-30
申请号：US16065435
申请日：2016-01-28
发明人： Vincent Nguyen , Sung Hsia Kuo , Ho M Lai
摘要： An example method includes linking a transmit line and receive line to a respective via, and printing two paths to each via, wherein each path is interrupted by two pairs of contacts. When a first resistor is in a first pair of contacts at a receive via, first signal is formed between a receive point of a first connector and the receive line. When a first capacitor is in first pair of contacts at a transmit via, second signal is formed between transmit point of first connector and the transmit line. When a second resistor is in second pair of contacts at receive via, third signal is formed between receive point of a second connector and the receive line. When a second capacitor is in second pair of contacts at transmit via, fourth signal is formed between a transmit point of second connector and the transmit line.
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公开(公告)号：US20180011716A1
公开(公告)日：2018-01-11
申请号：US15545628
申请日：2015-02-10
发明人： Vincent Nguyen , Hung Quoc Phu
CPC分类号： G06F9/4411 , G06F1/3287 , G06F9/4418 , G06F11/3034 , G06F11/3041 , G06F11/3051 , G06F13/385 , G06F13/4282
摘要： Example implementations relate to chipset reconfiguration based on device detection. For example, a method includes detecting, by a computing system, that a storage device is connected to an input/output (I/O) interface of the computing system, and reconfiguring a chipset of the computing system based on the detected storage device. The method also includes performing a power cycle on chipset standby power to trigger a chipset configuration reload.
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