公开(公告)号：US4948994A

公开(公告)日：1990-08-14

申请号：US254568

申请日：1988-10-07

申请人： Takashi Akioka ,  Atsuo Watanabe ,  Takahiro Nagano

发明人： Takashi Akioka ,  Atsuo Watanabe ,  Takahiro Nagano

IPC分类号： H03K17/04 ,  H03K17/00 ,  H03K17/0412 ,  H03K17/567 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K17/04126 ,  H03K2217/0036

摘要： A system providing a drive circuit for a bipolar transistor high in speed and low in power consumption even under a low source voltage using a MOSFET is disclosed. The base current of the bipolar transistor is supplied not by short-circuiting the collector and the base thereof by a MOSFET but from another base current source.

公开(公告)号：US07982266B2

公开(公告)日：2011-07-19

申请号：US11684032

申请日：2007-03-09

申请人： Atsuo Watanabe ,  Mitsutoshi Honda ,  Norio Ishitsuka ,  Masahiro Ito ,  Toshihito Tabata ,  Shinichi Kurita ,  Hidekazu Kamioka

发明人： Atsuo Watanabe ,  Mitsutoshi Honda ,  Norio Ishitsuka ,  Masahiro Ito ,  Toshihito Tabata ,  Shinichi Kurita ,  Hidekazu Kamioka

IPC分类号： H01L27/12

CPC分类号： H01L21/76286 ,  H01L29/7394 ,  H01L29/7824

摘要： A dielectrically isolated semiconductor device of high reliability is provided by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. The dielectrically isolated semiconductor device includes an SOI substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and an element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer, and which is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and a polycrystalline semiconductor layer formed between the second insulation films.

摘要翻译： 通过实现能够防止作为绝缘层的氧化膜由于氧化诱发应力而脱位的细微深元件隔离区域，提供高可靠性的介电隔离半导体器件。 介电隔离的半导体器件包括支撑有源元件层的SOI衬底，该有源元件层比经受施加到器件的最高电压的耗尽层的扩展距离更深，以及包围有源元件层的元件隔离区域。 元件隔离区域包含与绝缘层接触的深沟槽，并且在两个侧壁上填充有n个重掺杂层，每个与n重掺杂层相邻的第二绝缘膜和形成在第二绝缘层之间的多晶半导体层 第二绝缘膜。

公开(公告)号：US20100183157A1

公开(公告)日：2010-07-22

申请号：US12664557

申请日：2008-05-23

申请人： Atsuo Watanabe

发明人： Atsuo Watanabe

IPC分类号： H04R5/00

CPC分类号： H04S3/002 ,  H04R2400/03

摘要： In an audio signal reproduction device and an audio signal reproduction system of the present invention, an SLch sound is reproduced as a mixed sound that is adjusted appropriately by two speakers 5a, 5d located at Lch and SBLch speaker positions, and an SRch sound is reproduced as a mixed sound that is adjusted appropriately by two speakers 5b, 5e located at Rch and SBRch speaker positions. This configuration can achieve 5.1 ch virtual reproduction with high sound quality in which sounds for 5.1 channels of LPCM 7.1 ch audio information included in the contents are output as they are and sounds for the remaining 2 channels are reproduced artificially even if speakers compatible with the 5.1 ch sound field system are connected.

摘要翻译： 在本发明的音频信号再现装置和音频信号再现系统中，SLch声音被再现为由位于Lch和SBLch扬声器位置的两个扬声器5a，5d适当地调节的混合声音，并且再现SRch声音 作为由位于Rch和SBRch扬声器位置的两个扬声器5b，5e适当调节的混合声音。 该配置可以实现5.1声道高音质虚拟再现，其中包含在内容中的5.1声道LPCM 7.1声道信息的声音原样输出，其余2声道的声音即使人声兼容，即使扬声器与5.1 ch声场系统连接。

公开(公告)号：US07522692B2

公开(公告)日：2009-04-21

申请号：US11714856

申请日：2007-03-07

申请人： Seigoh Yukutake ,  Yasuyuki Kojima ,  Minehiro Nemoto ,  Masatsugu Amishiro ,  Takayuki Iwasaki ,  Shinichiro Mitani ,  Katsuhiro Furukawa ,  Chiyoshi Kamada ,  Atsuo Watanabe ,  Takayuki Oouchi ,  Nobuyasu Kanekawa

发明人： Seigoh Yukutake ,  Yasuyuki Kojima ,  Minehiro Nemoto ,  Masatsugu Amishiro ,  Takayuki Iwasaki ,  Shinichiro Mitani ,  Katsuhiro Furukawa ,  Chiyoshi Kamada ,  Atsuo Watanabe ,  Takayuki Oouchi ,  Nobuyasu Kanekawa

IPC分类号： H04L23/00 ,  H04B1/38 ,  H01L29/00

CPC分类号： H04L25/0266 ,  H01L2924/0002 ,  H04L25/0268 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L27/0002 ,  H04M11/06 ,  H01L2924/00

摘要： A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.

摘要翻译： 提供一种通信系统，包括收发机和应用控制器，用于通过收发信机发送和接收信号。 绝缘和分离收发器和应用控制器的隔离器包括在基板上彼此绝缘的初级和次级侧电路和用于在初级侧和第二侧之间传递信号的电容绝缘装置，同时将初级侧电路与次级侧隔离 电路。

公开(公告)号：US07355207B2

公开(公告)日：2008-04-08

申请号：US11135661

申请日：2005-05-24

申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

公开(公告)号：US20070023156A1

公开(公告)日：2007-02-01

申请号：US10571228

申请日：2004-09-01

申请人： Takahisa Hikita ,  Atsuo Watanabe

发明人： Takahisa Hikita ,  Atsuo Watanabe

IPC分类号： D21F3/00 ,  B32B3/00 ,  B32B5/02 ,  B32B27/12

CPC分类号： D21F3/0218 ,  D21F3/0227 ,  Y10S162/901 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T442/2369 ,  Y10T442/3854

摘要： A press belt (2) comprises both-end corresponding regions B positioned so as to correspond to both ends of a press roll (1) or a press shoe (3) in a width direction and having a small thickness and a center region A positioned between the both-end corresponding regions B and having a thickness larger than that of the both-end corresponding region B.

摘要翻译： 压榨带（2）包括两端对应的区域B，其定位成对应于压榨辊（1）或压板（3）在宽度方向上的两端，并且具有小的厚度，并且中心区域A定位 在两端对应区域B之间，其厚度大于两端对应区域B的厚度。

公开(公告)号：US20060191658A1

公开(公告)日：2006-08-31

申请号：US11416213

申请日：2006-05-03

申请人： Atsuo Watanabe ,  Takahisa Hikida ,  Atsushi Watanabe

发明人： Atsuo Watanabe ,  Takahisa Hikida ,  Atsushi Watanabe

IPC分类号： D03D15/00 ,  D21F3/00

CPC分类号： D21F3/0227 ,  C08G18/10 ,  C08G18/3808 ,  C08G18/3868 ,  C08G18/4854 ,  D21F3/0236 ,  Y10S162/901 ,  Y10T428/2457 ,  Y10T442/2041 ,  Y10T442/2066 ,  Y10T442/2098 ,  Y10T442/30 ,  C08G18/3814 ,  C08G18/6685

摘要： A papermaking belt, used for a shoe pressing belt, a calender belt and a sheet transfer belt, is prevented from cracking and inhibited from growth of a crack, and comprises a reinforcing substrate (6) embedded in a thermosetting polyurethane layer (7) so that the said reinforcing substrate (6) and the said thermosetting polyurethane layer (7) are integrated with each other and the outer peripheral surface and the inner peripheral surface of the belt are formed by polyurethane layers, the polyurethane layer forming the outer peripheral surface is made of a composition containing a urethane prepolymer having isocyanate groups on ends and a hardener containing dimethylthiotoluenediamine.

摘要翻译： 防止用于靴式压榨带，砑光带和片材转移带的造纸带被破裂并被抑制裂纹生长，并且包括嵌入热固性聚氨酯层（7）中的增强基材（6） 所述增强基板（6）和所述热固性聚氨酯层（7）彼此成一体，并且所述带的外周面和内周面由聚氨酯层形成，形成外周面的聚氨酯层为 由含有端部具有异氰酸酯基的氨基甲酸酯预聚物和含有二甲基硫代甲苯二胺的固化剂的组合物制成。

公开(公告)号：US20060071217A1

公开(公告)日：2006-04-06

申请号：US11206271

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

IPC分类号： H01L31/0312

CPC分类号： H01L21/823487 ,  H01L29/7722

摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

摘要翻译： 半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域 。 半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到 来自半导体基底的第二表面的栅极上升金属膜。

公开(公告)号：US06977522B1

公开(公告)日：2005-12-20

申请号：US10149763

申请日：1999-12-15

申请人： Fumio Murabayashi ,  Takashi Sase ,  Mutsumi Kikuchi ,  Atsuo Watanabe ,  Masatsugu Amishiro ,  Kenji Tabuchi

发明人： Fumio Murabayashi ,  Takashi Sase ,  Mutsumi Kikuchi ,  Atsuo Watanabe ,  Masatsugu Amishiro ,  Kenji Tabuchi

IPC分类号： G05B19/042 ,  G06F3/00 ,  H01L21/762 ,  H01L27/06 ,  H03K19/0175

CPC分类号： H01L21/76283 ,  G05B19/0428 ,  G05B2219/25428 ,  G05B2219/25462 ,  H01L27/0629 ,  H04L25/0266

摘要： A first converter circuit converts a state signal, whose level is constant or slowly varies during a predetermine period of time, into a pulse signal to allow the signal to propagate across an electrically insulating area. A second converter circuit converts the pulse signal, which has propagated through an insulating circuit, into the original state signal or a signal having the same characteristics as the original state signal.

摘要翻译： 第一转换器电路将预定时间段内的电平恒定或缓慢变化的状态信号转换成脉冲信号，以允许信号通过电绝缘区域传播。 第二转换器电路将已经通过绝缘电路传播的脉冲信号转换成原始状态信号或具有与原始状态信号相同特性的信号。

公开(公告)号：US06892582B1

公开(公告)日：2005-05-17

申请号：US09936480

申请日：1999-08-20

申请人： Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

发明人： Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

IPC分类号： B81B3/00 ,  B81B7/00 ,  G01L7/08 ,  G01L9/00 ,  H01L21/00

CPC分类号： B81C1/00333 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00293 ,  B81C2203/0145 ,  G01L9/0042 ,  G01L9/0073

摘要： The object of the present invention is to propose an etch channel sealing structure characterized by excellent impermeability to moisture and resistance to temporal change of the diaphragm in the pressure sensor produced according to the sacrificial layer etching technique, and to provide a pressure sensor characterized by excellent productivity and durability. After a very small gap is formed by the sacrificial layer etching technique, silicon oxide film is deposited by the CVD technique or the like, thereby sealing the etch channel. Further, impermeable thin film of polysilicon or the like is formed to cover the oxide film.This allows an etch channel sealing structure to be simplified in the pressure sensor produced according to the sacrificial layer etching technique, and prevents entry of moisture into the cavity, thereby improving moisture resistance. Moreover, sealing material with small film stress reduces temporal deformation of the diaphragm.

摘要翻译： 本发明的目的是提出一种蚀刻通道密封结构，其特征在于对根据牺牲层蚀刻技术制造的压力传感器中的防潮性和抗隔膜的时间变化具有优异的防渗性，并且提供一种特征在于优异的压力传感器 生产力和耐久性。 在通过牺牲层蚀刻技术形成非常小的间隙之后，通过CVD技术等沉积氧化硅膜，从而密封蚀刻通道。 此外，形成多晶硅等的不渗透性薄膜以覆盖氧化物膜。 这允许在根据牺牲层蚀刻技术产生的压力传感器中简化蚀刻通道密封结构，并且防止水分进入空腔，从而改善耐湿性。 此外，具有小膜应力的密封材料减小了隔膜的时间变形。