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    High breakdown voltage semiconductor circuit device
    1.
    发明授权
    High breakdown voltage semiconductor circuit device 失效
    高击穿电压半导体电路器件

    公开(公告)号：US08134207B2

    公开(公告)日：2012-03-13

    申请号：US12028157

    申请日：2008-02-08

    Applicant: Atsuo Watanabe

    Inventor： Atsuo Watanabe

    IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/70

    CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7824

    Abstract: In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 μm or more.

    Abstract translation: 在集成在SOI衬底上的元件之间的高耐压电压半导体元件中，其中在由衬底的氧化物层和由元件有源层形成的漏极区域之间共享额定电压，实现高集成度和高​​击穿电压，同时还确保 适用于实际实施和实际应用。 通过在漏极区的表面形成与漏极区相反的导电类型的电浮置层，实现了高的击穿电压，而不会妨碍元件的尺寸减小。 此外，通过将SOI衬底的元件有源层的厚度设定为30μm以上，将嵌入氧化物层的厚度减小到适于实际实现和实际应用的水平。

    A/V amplifier and method for driving the same
    2.
    发明授权
    A/V amplifier and method for driving the same 有权
    A / V放大器及其驱动方法

    公开(公告)号：US08081781B2

    公开(公告)日：2011-12-20

    申请号：US11814791

    申请日：2006-02-23

    Applicant: Atsuo Watanabe

    Inventor： Atsuo Watanabe

    IPC: H02B1/00

    CPC classification number: H04S5/02 ,  H03F3/181 ,  H03F3/217 ,  H03F3/68 ,  H03F2200/03

    Abstract: For achieving an audio reproduction with high sound quality, in a multi-channel A/V amplifier, front speakers are driven with a parallel-drive bi-amplifier arrangement upon stereo reproduction. In the case of the multi-channel reproduction mode, the switching circuit allows an output signal of each channel of the decoder to be sent to speakers via amplifiers for each channel in one-to-one correspondence. On the other hand, in the case of the 2-channel stereo reproduction mode, the switching circuit allows at least two amplifiers among the plurality of amplifiers to be connected in parallel between the output signal for each of the channels L and R of the decoder and the speakers for each of the channels L and R, and also allows the timing of the output signals of the respective amplifiers to be varied.

    Abstract translation: 为了实现高音质的音频再现，在多声道A / V放大器中，在立体声再现时，前置扬声器由并行驱动双放大器布置驱动。 在多声道再现模式的情况下，切换电路允许解码器的每个声道的输出信号通过一个对应的每个声道的放大器发送到扬声器。 另一方面，在2声道立体声再现模式的情况下，切换电路允许多个放大器中的至少两个放大器并联连接在解码器的每个通道L和R的输出信号之间 以及每个通道L和R的扬声器，并且还允许各个放大器的输出信号的定时改变。

    Method for manufacturing silicon carbide semiconductor device
    3.
    发明申请
    Method for manufacturing silicon carbide semiconductor device 有权
    碳化硅半导体器件的制造方法

    公开(公告)号：US20080153216A1

    公开(公告)日：2008-06-26

    申请号：US12071186

    申请日：2008-02-19

    Applicant: Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

    Inventor： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ohyanagi ,  Atsuo Watanabe

    IPC: H01L21/82

    CPC classification number: H01L29/1608 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/66068 ,  H01L29/8083

    Abstract: A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.

    Abstract translation: 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

    SIC semiconductor device and method for manufacturing the same
    4.
    发明申请
    SIC semiconductor device and method for manufacturing the same 有权
    SIC半导体器件及其制造方法

    公开(公告)号：US20070241338A1

    公开(公告)日：2007-10-18

    申请号：US11783611

    申请日：2007-04-10

    Applicant: Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

    Inventor： Tsuyoshi Yamamoto ,  Toshio Sakakibara ,  Hiroki Nakamura ,  Toshiyuki Morishita ,  Takasumi Ooyanagi ,  Atsuo Watanabe

    IPC: H01L31/0312

    CPC classification number: H01L29/1608 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/8083 ,  H01L29/872

    Abstract: A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.

    Abstract translation: SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。

    Semiconductor devices
    5.
    发明申请
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US20070221924A1

    公开(公告)日：2007-09-27

    申请号：US11802810

    申请日：2007-05-25

    Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

    Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

    IPC: H01L29/772

    CPC classification number: H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

    Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

    Abstract translation: 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。

    Field effect transistor
    7.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号：US07067878B2

    公开(公告)日：2006-06-27

    申请号：US09964809

    申请日：2001-09-28

    Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe

    Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe

    IPC: H01L31/119

    CPC classification number: H01L29/66659 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

    Abstract: A MOS field effect transistor. A field relaxation layer of a gate overlap structure is disposed in contact with a drain region for the purpose of relaxation of the electric field by increasing a distance between the field relaxation layer and a high-density layer. The electric field relaxation can further be promoted because the equipotential lines are bent by a gate insulation film. A punch-through stopper layer of a gate overlap structure is disposed in contact with a source region for suppressing spreading of a depletion layer toward the source region. The length of a gate electrode can be realized in a miniaturized size.

    Abstract translation: MOS场效应晶体管。 为了通过增加场弛豫层和高密度层之间的距离来放电电场，栅极重叠结构的场弛豫层被设置为与漏区接触。 由于等电位线被栅极绝缘膜弯曲，所以可以进一步促进电场弛豫。 栅极重叠结构的穿通停止层设置成与用于抑制耗尽层朝向源极区域扩散的源极区域接触。 可以以小型化的尺寸实现栅电极的长度。

    Semiconductor devices
    8.
    发明申请
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US20060060884A1

    公开(公告)日：2006-03-23

    申请号：US11138298

    申请日：2005-05-27

    Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

    Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

    IPC: H01L29/74

    CPC classification number: H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

    Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

    Abstract translation: 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。

    Insulated gate field effect transistor and semiconductor integrated circuit
    10.
    发明授权
    Insulated gate field effect transistor and semiconductor integrated circuit 有权
    绝缘栅场效应晶体管和半导体集成电路

    公开(公告)号：US06657257B2

    公开(公告)日：2003-12-02

    申请号：US09829582

    申请日：2001-04-09

    Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe

    Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe

    IPC: H01L2701

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824

    Abstract: According to the present invention, there is provided an N-type insulated gate field effect transistor using an SOI substrate of which Si layer as a device formation area is N-type. The SOI substrate provided as the device formation area has the N-type semiconductor region, which has an impurity concentration higher than the impurity concentration of the device formation area, formed so that the N-type semiconductor region is contacted to a part of a gate insulating film and a field silicon oxide film formed between a source electrode and a drain electrode, and extends to be contacted to the N-type semiconductor diffusion layer contacted to the drain electrode. According to the above arrangement, the on-state breakdown can be remarkably improved.

    Abstract translation: 根据本发明，提供一种使用其作为器件形成区域的Si层作为N型的SOI衬底的N型绝缘栅场效应晶体管。 作为器件形成区域提供的SOI衬底具有N型半导体区域，其具有高于器件形成区域的杂质浓度的杂质浓度，以使得N型半导体区域与栅极的一部分接触 绝缘膜和在源电极和漏电极之间形成的场氧化硅膜，并且延伸以与与漏电极接触的N型半导体扩散层接触。 根据上述结构，可以显着提高导通状态的故障。

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