公开(公告)号：US5680363A

公开(公告)日：1997-10-21

申请号：US632279

申请日：1996-04-15

申请人： Katsumi Dosaka ,  Masaki Kumanoya

发明人： Katsumi Dosaka ,  Masaki Kumanoya

IPC分类号： G06F12/08 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

CPC分类号： G11C7/103 ,  G11C7/1051 ,  G11C7/1078

摘要： In an operation of transferring data between a DRAM array and an SRAM array through a bidirectional transfer gate circuit, data blocks on a selected one in the DRAM array are sequentially selected in a high speed mode, word lines are sequentially selected in the SRAM array, so that data is transferred in a time division multiplexing manner between the DRAM array and the SRAM array in units of data block. A cache block size in a semiconductor memory device containing a cache can be externally changed depending on the application with the internal configuration maintained unchangedly.

摘要翻译： 在通过双向传输门电路在DRAM阵列和SRAM阵列之间传送数据的操作中，DRAM阵列中所选择的数据块以高速模式顺序地选择，在SRAM阵列中依次选择字线， 使得数据以数据块为单位在DRAM阵列和SRAM阵列之间以时分复用方式传送。 包含缓存的半导体存储器件中的高速缓存块大小可以根据内部配置保持不变的应用而外部改变。

公开(公告)号：US5650968A

公开(公告)日：1997-07-22

申请号：US655322

申请日：1996-05-21

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5623454A

公开(公告)日：1997-04-22

申请号：US599265

申请日：1996-02-09

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5184321A

公开(公告)日：1993-02-02

申请号：US821875

申请日：1992-01-16

申请人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

发明人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

IPC分类号： G11C11/4074 ,  G11C11/408

CPC分类号： G11C11/4074 ,  G11C11/408 ,  Y10S257/92

摘要： A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

摘要翻译： 多个存储器阵列（10a，10b）形成在半导体芯片（CH）上。 外围电路（60）布置在多个存储器阵列（10a，10b）的中心部分。 在半导体芯片（CH）的两端形成有多个焊盘（PD; p1差异p18）。 多个存储器阵列（10a，10b）由预定层形成（101差异109）。 要连接在多个焊盘（PD; p1 DIFFERENCE p18）和外围电路（60）之间的多个互连（L）被设置成跨越多个存储器阵列。 多个互连（L）由除预定的互连层之外的层（112; 113）形成。

公开(公告)号：US4961167A

公开(公告)日：1990-10-02

申请号：US381347

申请日：1989-07-18

申请人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

发明人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

IPC分类号： G11C11/4074

CPC分类号： G11C11/4074

摘要： A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal. The above construction contributes to a reduced power consumption in the dynamic random access memory.

摘要翻译： 一种具有自刷新功能的动态随机存取存储器，其包括适于被间歇地驱动以向半导体衬底（15）施加偏置电位的衬底偏置发生器（100）。 该存储装置包括用于响应于外部刷新指令信号产生内部刷新指令信号（phi S）的电路（91），响应于内部刷新指令信号产生刷新的电路（92,93） 使能信号（phi R）以预定的间隔间歇地连接到响应于刷新使能信号刷新存储器单元中的数据的电路（94,95,96,98）和响应于电路（99）的电路（99） 对于内部刷新指令信号和刷新使能信号，在与产生刷新使能信号的周期相同的周期中，仅在比生成刷新使能信号的周期短的时间内激活衬底偏置发生器。 上述结构有助于动态随机存取存储器中的功耗降低。

公开(公告)号：US4961007A

公开(公告)日：1990-10-02

申请号：US337218

申请日：1989-04-12

申请人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Youichi Tobita

发明人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Youichi Tobita

IPC分类号： G11C11/408 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： G05F3/205 ,  H02M3/07

摘要： A substrate bias potential generator for biasing a semiconductor substrate to a predetermined potential includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate, whereby consumption of power in the substrate bias potential generator is reduced. The alternative operation of the bias generating circuits each activated by a pulse signal train is performed by using a first insulated gate transistor having a gate electrode connected to the semiconductor substrate, a second insulated gate transistor having a gate electrode for receiving the reference potential, an amplifier for differentially amplifying outputs of the first and second insulated gate transistors, an insulated gate transistor for charging an output of the amplifier to a predetermined potential when the amplifier is activated, and a circuit for transmitting the output of the differential amplifier to the first and second bias potential generating circuits. The differential amplifier is activated in response to an activation signal of a pulse train whereby an activation signal corresponding to the pulse train is transmitted to either substrate bias potential generating circuit.

摘要翻译： 用于将半导体衬底偏置到预定电位的衬底偏置电位发生器包括根据衬底的电位交替地操作的第一和第二衬底偏置产生电路，由此降低衬底偏置电位发生器中的功率消耗。 通过使用具有连接到半导体衬底的栅电极的第一绝缘栅极晶体管，具有用于接收参考电位的栅电极的第二绝缘栅极晶体管，执行由脉冲信号列激活的偏置产生电路的替代操作， 放大器，用于差分放大第一和第二绝缘栅极晶体管的输出;绝缘栅极晶体管，用于在放大器被激活时将放大器的输出充电到预定电位;以及电路，用于将差分放大器的输出传输到第一和第二绝缘栅极晶体管， 第二偏置电位发生电路。 差分放大器响应于脉冲串的激活信号被激活，由此将对应于脉冲串的激活信号传输到任一衬底偏置电位产生电路。

公开(公告)号：US4933907A

公开(公告)日：1990-06-12

申请号：US278552

申请日：1988-12-01

申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu ,  Yoichi Tobita

发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu ,  Yoichi Tobita

IPC分类号： G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A dynamic random access memory having a self-refresh mode comprises a memory array partitioned into four groups in which control are respectively performed and a partial activation control circuit. The four groups in the memory array are alternately refreshed two by two in an operation under the self-refresh mode. As a result, each group in the memory array is refreshed at a time interval of two times a conventional refresh interval, so that the power consumption is decreased.

摘要翻译： 具有自刷新模式的动态随机存取存储器包括分为四组的存储器阵列，其中分别执行控制和部分激活控制电路。 存储器阵列中的四组在自刷新模式下的操作中被两个两个地刷新。 结果，存储器阵列中的每个组以传统刷新间隔的两倍的时间间隔被刷新，使得功耗降低。

公开(公告)号：US06170036A

公开(公告)日：2001-01-02

申请号：US08780066

申请日：1996-12-23

申请人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

发明人： Yasuhiro Konishi ,  Katsumi Dosaka ,  Kouji Hayano ,  Masaki Kumanoya ,  Akira Yamazaki ,  Hisashi Iwamoto

IPC分类号： G06F1300

CPC分类号： G11C7/1006 ,  G06F12/0893 ,  G11C7/103 ,  G11C7/1045 ,  G11C11/005 ,  G11C2207/2254

摘要： A semiconductor memory device is configured to include a static random access memory (SRAM) array and a dynamic random access memory (DRAM) array. The memory device includes an internal data line which enables the transfer of data blocks between the SRAM and DRAM arrays. Data transfer circuitry is provided separately from the internal data line and includes a latch circuit for latching the data to be transferred. The data transfer circuitry is responsive to a transfer designating signal.

摘要翻译： 半导体存储器件被配置为包括静态随机存取存储器（SRAM）阵列和动态随机存取存储器（DRAM）阵列。 存储器件包括内部数据线，其能够在SRAM和DRAM阵列之间传输数据块。 数据传输电路与内部数据线分开提供，并且包括用于锁存要传送的数据的锁存电路。 数据传输电路响应传输指定信号。

公开(公告)号：US6026029A

公开(公告)日：2000-02-15

申请号：US865310

申请日：1997-05-29

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5848004A

公开(公告)日：1998-12-08

申请号：US625578

申请日：1996-03-28

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.