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    Power management for circuits with inactive state data save and restore scan chain
    21.
    发明授权
    Power management for circuits with inactive state data save and restore scan chain 有权
    具有非活动状态数据的电路的电源管理保存并恢复扫描链

    公开(公告)号：US07269780B2

    公开(公告)日：2007-09-11

    申请号：US10674951

    申请日：2003-09-30

    申请人： Yukio Arima ,  Koichiro Ishibashi ,  Takahiro Yamashita

    发明人： Yukio Arima ,  Koichiro Ishibashi ,  Takahiro Yamashita

    IPC分类号： G11C29/00

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172

    摘要： An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.

    摘要翻译： 集成电路装置包括至少一个功能模块，其与保存时钟信号同步地输出保存数据;电源控制单元，选择功能模块之一，并控制对所选择的功能模块的电源的停止和恢复; 保存数据存储单元，其存储从由电源控制单元选择的功能模块输出的保存数据;以及错误检查和校正单元，当保存数据是存储数据时，对存储在保存数据存储单元中的保存数据进行错误校验和校正 与恢复时钟信号同步地恢复到功能模块。

    Acs circuit
    22.
    发明申请
    Acs circuit 有权
    Acs电路

    公开(公告)号：US20070200739A1

    公开(公告)日：2007-08-30

    申请号：US10591457

    申请日：2004-12-15

    申请人： Yukio Arima ,  Akira Yamamoto

    发明人： Yukio Arima ,  Akira Yamamoto

    IPC分类号： H03M13/41

    CPC分类号： H03M13/4107

    摘要： An ACS circuit includes: a basic DPM retaining section (11) for retaining basic DPMs (differential path metrics); a basic DPM calculating section (12) for calculating the basic DPMs; a reference DPM calculating section (13) for calculating reference DPMs, which are DPMs other than the basic DPMs; a basic DBM calculating section (14) for calculating basic DBMs (differential branch metrics), which are DBMs necessary for calculating the basic DPMs; and a path selecting section (15) for selecting the most likely paths for Viterbi decoding in accordance with the basic DPMs, the reference DPMs and the basic DBMs. The basic DPM calculating section (12) calculates new basic DPMs in accordance with the basic DPMs, the reference DPMs, the basic DBMs, and the results of the most likely path selection by the path selecting section (15).

    摘要翻译： ACS电路包括：用于保持基本DPM（差分路径量度）的基本DPM保持部分（11）; 用于计算基本DPM的基本DPM计算部分（12）; 用于计算参考DPM的参考DPM计算部分（13），其是除基本DPM之外的DPM; 用于计算基本DBM（差分分支量度）的基本DBM计算部分（14），其是计算基本DPM所需的DBM; 以及用于根据基本DPM，参考DPM和基本DBM选择用于维特比解码的最可能路径的路径选择部分（15）。 基本DPM计算部分（12）根据路径选择部分（15）根据基本DPM，参考DPM，基本DBM以及最可能的路径选择的结果来计算新的基本DPM。

    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit
    24.
    发明授权
    Network unit with power saving mode inhibit based on interconnection relationship to neighboring nodes which is stored on the unit 有权
    具有省电模式的网络单元基于与存储在单元上的相邻节点的互连关系而禁止

    公开(公告)号：US06604201B1

    公开(公告)日：2003-08-05

    申请号：US09428277

    申请日：1999-10-27

    申请人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    发明人： Satoshi Takahashi ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Tadahiro Yoshida ,  Yutaka Terada ,  Yukio Arima ,  Takashi Hirata ,  Yoshihide Komatsu

    IPC分类号： G06F132

    CPC分类号： H04L12/12 ,  Y02D50/20 ,  Y02D50/40

    摘要： A power-saving network unit, which is connected to a network made up of a plurality of power-saving network units, includes: network monitoring means; network information memory; power-saving mode setting means; peripheral I/O interface; and digital processor. The network monitoring means monitors a topology of the network, or the interconnection relationship among the power-saving network units. Every time the network has been modified, the network monitoring means stores the modified network topology on the network information memory. The power-saving mode setting means receives the network information stored on the network information memory. If the power-saving network unit is a master or relay node in the network, then the power-saving mode setting means locks the peripheral I/O interface and digital processor of the power-saving network unit to the normal operation mode and prohibits these sections from entering the power-saving mode.

    摘要翻译： 连接到由多个省电网络单元组成的网络的节电网单元包括：网络监控装置; 网络信息记忆; 省电模式设定手段; 外设I / O接口; 和数字处理器。 网络监控装置监控网络的拓扑结构，或节能网络单元之间的互连关系。 每当网络被修改时，网络监控装置将修改的网络拓扑存储在网络信息存储器上。 省电模式设置装置接收存储在网络信息存储器上的网络信息。 如果省电网络单元是网络中的主节点或中继节点，则省电模式设置装置将节电网络单元的外围I / O接口和数字处理器锁定到正常操作模式，并禁止这些 部分进入省电模式。

    PLL CIRCUIT
    25.
    发明申请
    PLL CIRCUIT 审中-公开
    PLL电路

    公开(公告)号：US20110115531A1

    公开(公告)日：2011-05-19

    申请号：US13014362

    申请日：2011-01-26

    申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

    IPC分类号： H03L7/095 ,  H03B19/00 ,  H03L7/10

    CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

    摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

    摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

    ACS circuit
    26.
    发明授权
    ACS circuit 有权
    ACS电路

    公开(公告)号：US07779339B2

    公开(公告)日：2010-08-17

    申请号：US10591457

    申请日：2004-12-15

    申请人： Yukio Arima ,  Akira Yamamoto

    发明人： Yukio Arima ,  Akira Yamamoto

    IPC分类号： H03M13/03

    CPC分类号： H03M13/4107

    摘要： An ACS circuit includes: a basic DPM retaining section (11) for retaining basic DPMs (differential path metrics); a basic DPM calculating section (12) for calculating the basic DPMs; a reference DPM calculating section (13) for calculating reference DPMs, which are DPMs other than the basic DPMs; a basic DBM calculating section (14) for calculating basic DBMs (differential branch metrics), which are DBMs necessary for calculating the basic DPMs; and a path selecting section (15) for selecting the most likely paths for Viterbi decoding in accordance with the basic DPMs, the reference DPMs and the basic DBMs. The basic DPM calculating section (12) calculates new basic DPMs in accordance with the basic DPMs, the reference DPMs, the basic DBMs, and the results of the most likely path selection by the path selecting section (15).

    摘要翻译： ACS电路包括：用于保持基本DPM（差分路径量度）的基本DPM保持部分（11）; 用于计算基本DPM的基本DPM计算部分（12）; 用于计算参考DPM的参考DPM计算部分（13），其是除基本DPM之外的DPM; 用于计算基本DBM（差分分支量度）的基本DBM计算部分（14），其是计算基本DPM所需的DBM; 以及用于根据基本DPM，参考DPM和基本DBM选择用于维特比解码的最可能路径的路径选择部分（15）。 基本DPM计算部分（12）根据路径选择部分（15）根据基本DPM，参考DPM，基本DBM以及最可能的路径选择的结果来计算新的基本DPM。

    Frequency modulation circuit
    27.
    发明授权
    Frequency modulation circuit 有权
    频率调制电路

    公开(公告)号：US07233215B2

    公开(公告)日：2007-06-19

    申请号：US11000224

    申请日：2004-12-01

    申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

    发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

    IPC分类号： H03C3/00

    CPC分类号： H04B15/02 ,  H03K7/06 ,  H04B2215/067

    摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

    摘要翻译： 频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

    Bus transfer apparatus
    30.
    发明授权
    Bus transfer apparatus 失效
    总线传送装置

    公开(公告)号：US06513087B1

    公开(公告)日：2003-01-28

    申请号：US09570466

    申请日：2000-05-12

    申请人： Yukio Arima

    发明人： Yukio Arima

    IPC分类号： G06F1300

    CPC分类号： G06F13/405

    摘要： A bus transfer apparatus for receiving a packet and repeating the received packet, in which the packet includes a PREFIX portion indicating the head of the packet, a DATA portion storing data, and an END portion indicating the end of the packet, includes a control circuit for receiving the packet and outputting the PREFIX portion of the packet as a control signal; a counter for counting a time period during which the control circuit outputs the PREFIX portion, and outputting a counter full signal when the time period reaches a predetermined lower limit; an address pointer for determining a read address in response to the counter full signal; a data buffer for holding the DATA portion of the packet and outputting the DATA portion in accordance with the read address; an encoder for converting the DATA portion output from the data buffer to a predetermined format; and a first selector for selecting either the PREFIX portion output from the control circuit or the DATA portion output from the encoder. The output signal from the first selector is switched from the PREFIX portion of the packet to the DATA portion of the packet after the counter full signal is output from the counter.

    摘要翻译： 一种用于接收分组并重复所接收的分组的总线传送装置，其中所述分组包括指示分组的头部的PREFIX部分，存储数据的DATA部分和指示分组结束的END部分，包括控制电路 用于接收分组并输出分组的PREFIX部分作为控制信号; 用于计数控制电路输出PREFIX部分的时间段的计数器，以及当所述时间段达到预定下限时输出计数器全信号; 用于响应于所述计数器全信号确定读地址的地址指针; 数据缓冲器，用于保持数据包的DATA部分并根据读取的地址输出DATA部分; 用于将从数据缓冲器输出的DATA部分转换为预定格式的编码器; 以及第一选择器，用于选择从控制电路输出的PREFIX部分或从编码器输出的DATA部分。 在从计数器输出计数器完整信号之后，来自第一选择器的输出信号从分组的PREFIX部分切换到分组的DATA部分。