公开(公告)号：US07898305B2

公开(公告)日：2011-03-01

申请号：US12651061

申请日：2009-12-31

申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

公开(公告)号：US07746132B2

公开(公告)日：2010-06-29

申请号：US12066000

申请日：2006-07-27

申请人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

发明人： Tatsuo Okamoto ,  Yukio Arima ,  Tsuyoshi Ebuchi ,  Kyoko Hirata

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/1976

摘要： A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

摘要翻译： PLL包括电流控制振荡器（18），用于基于基于参考时钟信号和反馈时钟信号之间的相位差产生的电流信号，电流源（28）和初始化开关（18）来产生输出时钟信号 （26），用于基于所述初始化信号执行打开/关闭操作，所述初始化开关串联插入到所述电流控制振荡器（18）和所述电流源（28）的输入端子。

公开(公告)号：US20050135505A1

公开(公告)日：2005-06-23

申请号：US11000224

申请日：2004-12-01

申请人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

发明人： Tsuyoshi Ebuchi ,  Takefumi Yoshikawa ,  Yukio Arima

IPC分类号： H03C3/00 ,  H03K7/06 ,  H03L7/093 ,  H04B15/02 ,  H04B3/46

CPC分类号： H04B15/02 ,  H03K7/06 ,  H04B2215/067

摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

摘要翻译： 频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

公开(公告)号：US5293326A

公开(公告)日：1994-03-08

申请号：US719510

申请日：1991-06-24

申请人： Yukio Arima ,  Hiroaki Yanagimoto ,  Yuichi Kunitomo ,  Shouya Makihara ,  Tetsuyoshi Tominaga

发明人： Yukio Arima ,  Hiroaki Yanagimoto ,  Yuichi Kunitomo ,  Shouya Makihara ,  Tetsuyoshi Tominaga

IPC分类号： G01N29/06 ,  G01N29/44 ,  G01Q10/06 ,  G01Q30/04 ,  G01Q80/00 ,  G01Q90/00 ,  G01S7/52 ,  G01N29/00 ,  G09G5/00

CPC分类号： G01S7/52074 ,  G01N29/0609 ,  G01N29/0645 ,  B82Y35/00 ,  G01N2291/02854

摘要： An ultrasonic inspection and imaging instrument is characterized by storing reduced image examples (images by means of reduced image display data obtained by scaling down picture display data) of an ultrasonic measurement picture beforehand, together with measurement conditions at the time the measurement picture is obtained prior to a scale-down imaging process. When the measurement is started or the measurement conditions are otherwise changed, the measurement conditions are set as those obtained from the measurement picture prior to the scale-down processing with one of the reduced image examples thus selected as an index while a list of image examples is indicated on a display and read from a memory unit for ultrasonic measuring purposes. When a reduced image example or what is similar to the example desired by an operator is selected, proper measurement conditions are automatically set in the ultrasonic inspection and imaging instrument. When the operator wants to change or switch the measurement picture, moreover, he/she is able to make ultrasonic measurement on confirming what the subsequent image is like or what an image is desired to be selected by means of the reduced image example beforehand.

摘要翻译： 超声波检查和成像仪器的特征在于预先存储超声波测量图像的缩小图像示例（通过缩小图像显示数据获得的缩小图像显示数据的图像）以及在获得测量图像时的测量条件 到缩小成像过程。 当测量开始或测量条件另外改变时，测量条件被设置为在缩小处理之前从测量图像获得的测量条件，其中一个缩小图像示例被选择为索引，而图像示例列表 在显示器上指示并从用于超声波测量目的的存储器单元读取。 当选择缩小的图像示例或类似于操作者期望的示例时，在超声波检查和成像仪器中自动设置适当的测量条件。 此外，当操作者想要改变或切换测量图像时，他/她能够通过预先通过缩小的图像实例来确认随后的图像是什么样的或希望选择什么图像来进行超声波测量。

公开(公告)号：US08300755B2

公开(公告)日：2012-10-30

申请号：US12602751

申请日：2007-11-30

申请人： Yukio Arima

发明人： Yukio Arima

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/089 ,  H03L7/091

摘要： A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock.

摘要翻译： 比较周期确定器（110）在包括参考时钟的上升沿出现的定时的比较周期中检测接收数据是否发生变化。 相位确定器（120）确定接收数据的上升沿是否位于参考时钟之前或之后，并且确定接收数据的下降沿是否位于参考时钟之前或之后，并输出第一确定信号和 指示各个确定的结果的第二确定信号。 同步数据生成器（130）与同步时钟同步地输出具有比较周期确定器（110）的检测结果的电平和相位确定器（120）的输出作为同步数据的信号。

公开(公告)号：US08149974B2

公开(公告)日：2012-04-03

申请号：US12374743

申请日：2006-11-15

申请人： Yukio Arima ,  Akinori Shinmyo ,  Toru Iwata

发明人： Yukio Arima ,  Akinori Shinmyo ,  Toru Iwata

IPC分类号： H04L7/00

CPC分类号： H03L7/089 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0337

摘要： A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.

摘要翻译： 比较周期检测单元（11）将第一时钟信号的上升沿和第二时钟信号的上升沿之间的周期定义为比较周期，并且在第一时钟信号的上升沿期间检测数据信号的转换是否存在 比较期 相位关系检测单元（12）检测数据信号和参考时钟信号之间的相位关系，并且当比较周期检测单元（11）在比较期间检测到数据信号的转变时，输出相位关系的检测结果 期。

公开(公告)号：US07970092B2

公开(公告)日：2011-06-28

申请号：US12090774

申请日：2006-03-10

申请人： Yukio Arima ,  Toru Iwata ,  Makoto Miyake ,  Takefumi Yoshikawa

发明人： Yukio Arima ,  Toru Iwata ,  Makoto Miyake ,  Takefumi Yoshikawa

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891

摘要： A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

摘要翻译： 用于高速数据通信的定时恢复过程中的相位比较处理定义数据窗口并将窗口中的时钟的相位与数据边缘的相位进行比较，以实现并行处理，其中相位比较和 执行数据边缘位于窗口内的处理是彼此并行执行的，并且仅当数据边缘位于窗口内时才输出相位比较结果。 利用这种配置，可以在不需要高精度延迟电路的情况下，无误地执行精确的相位比较处理。

公开(公告)号：US07167033B2

公开(公告)日：2007-01-23

申请号：US11154114

申请日：2005-06-15

申请人： Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

发明人： Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

IPC分类号： H03K3/356 ,  H03K3/286

CPC分类号： H03K3/0375 ,  H03K3/356156 ,  H03K3/3565 ,  H03K17/162 ,  H03K17/165 ,  H03K19/00338

摘要： A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.

摘要翻译： 已经公开了一种数据保持电路，其中即使发生软错误，也可以进行校正，可以保持正常值，配置简单，并且能够进行高速操作。 在该电路中，当要放出的数据发生软错误时，通过上拉路径或下拉路径进行校正，并且当在上拉路径中的数据或 下拉路径，防止上拉路径或下拉路径中的误差数据彼此相互影响，以及关闭校正功能以防止对数据的影响。

公开(公告)号：US06631486B1

公开(公告)日：2003-10-07

申请号：US09405015

申请日：1999-09-27

申请人： Yoshihide Komatsu ,  Tadahiro Yoshida ,  Yukio Arima

发明人： Yoshihide Komatsu ,  Tadahiro Yoshida ,  Yukio Arima

IPC分类号： G01R3128

CPC分类号： G01R31/31905 ,  G01R31/31926

摘要： A test enable signal Data_En is output from a data generator 11 in a tester 10 to a device under a test (DUT) 20. In the DUT 20, a first logic circuit 21 converts a signal pattern with an ordinary transfer rate, which has been stored on a register 28, into a high-transfer-rate signal pattern SpeedData_Tx with a high rate. And a transmitter 22 transmits the high-transfer-rate signal. During a test, the high-transfer-rate signal transmitted is received by, a receiver 23 with a switch 24 turned ON. Then, the high-transfer-rate signal received is output to a second logic circuit 26, which converts the high-transfer-rate signal into a low-transfer-rate signal Data_Rx with an ordinary rate. Finally, the low-transfer-rate signal is output to the tester 10 and compared to an expected value thereof by a comparator 12. In this manner, a semiconductor device operating at a high speed can be tested using a tester operating at a lower speed.

摘要翻译： 测试使能信号Data_En从测试器10中的数据发生器11输出到被测设备（DUT）20。在DUT 20中，第一逻辑电路21以一般传输速率转换信号模式 存储在寄存器28中，以高速率转换成高传输速率信号模式SpeedData_Tx。 并且发射机22发送高传输速率信号。 在测试期间，传输的高传输速率信号由开关24接通的接收机23接收。 然后，所接收的高传输速率信号被输出到第二逻辑电路26，第二逻辑电路26将高传输速率信号以普通速率转换成低传输速率信号Data_Rx。 最后，将低传输速率信号输出到测试器10，并通过比较器12与其期望值进行比较。以这种方式，可以使用以较低速度操作的测试仪来测试以高速工作的半导体器件 。

公开(公告)号：US06505303B1

公开(公告)日：2003-01-07

申请号：US09464769

申请日：1999-12-16

申请人： Yukio Arima

发明人： Yukio Arima

IPC分类号： G06F132

CPC分类号： H04L49/254 ,  H04L49/351

摘要： In a network system, the data transfer efficiency attained when a given port is placed in a sleeping state is improved. A first node having received a request for setting a port thereof to a sleeping state notices transition to a sleeping state from that port. A second node having received notice of the transition to a sleeping state sets a port thereof at which the notice is received to a sleeping state, sends the node number of a node to which data is transferable from that port as communication disable node information from another port thereof, and forms a local network. In this manner, data transfer can be conducted independently within the local network.

摘要翻译： 在网络系统中，当给定端口处于睡眠状态时获得的数据传输效率得到改善。 已经接收到将其端口设置为睡眠状态的请求的第一节点通知从该端口转换到睡眠状态。 已经接收到转移到休眠状态的通知的第二节点将其中接收通知的端口设置为休眠状态，将来自该端口的数据可传输的节点的节点号作为来自另一个的通信禁用节点信息 端口，并形成本地网络。 以这种方式，可以在本地网络内独立进行数据传输。